f28b958cbf
"hw/xen/xen_pt.h" requires "hw/xen/xen_native.h" which is target specific. It also declares IGD methods, which are not target specific. Target-agnostic code can use IGD methods. To allow that, extract these methos into a new "hw/xen/xen_igd.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> Message-Id: <20231114143816.71079-18-philmd@linaro.org>
414 lines
13 KiB
C
414 lines
13 KiB
C
/*
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* graphics passthrough
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/xen/xen_pt.h"
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#include "hw/xen/xen_igd.h"
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#include "xen-host-pci-device.h"
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static unsigned long igd_guest_opregion;
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static unsigned long igd_host_opregion;
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#define XEN_PCI_INTEL_OPREGION_MASK 0xfff
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typedef struct VGARegion {
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int type; /* Memory or port I/O */
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uint64_t guest_base_addr;
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uint64_t machine_base_addr;
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uint64_t size; /* size of the region */
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int rc;
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} VGARegion;
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#define IORESOURCE_IO 0x00000100
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#define IORESOURCE_MEM 0x00000200
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static struct VGARegion vga_args[] = {
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{
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.type = IORESOURCE_IO,
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.guest_base_addr = 0x3B0,
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.machine_base_addr = 0x3B0,
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.size = 0xC,
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.rc = -1,
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},
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{
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.type = IORESOURCE_IO,
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.guest_base_addr = 0x3C0,
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.machine_base_addr = 0x3C0,
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.size = 0x20,
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.rc = -1,
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},
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{
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.type = IORESOURCE_MEM,
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.guest_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
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.machine_base_addr = 0xa0000 >> XC_PAGE_SHIFT,
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.size = 0x20,
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.rc = -1,
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},
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};
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/*
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* register VGA resources for the domain with assigned gfx
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*/
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int xen_pt_register_vga_regions(XenHostPCIDevice *dev)
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{
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int i = 0;
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if (!is_igd_vga_passthrough(dev)) {
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return 0;
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}
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for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
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if (vga_args[i].type == IORESOURCE_IO) {
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vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
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vga_args[i].guest_base_addr,
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vga_args[i].machine_base_addr,
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vga_args[i].size, DPCI_ADD_MAPPING);
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} else {
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vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
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vga_args[i].guest_base_addr,
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vga_args[i].machine_base_addr,
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vga_args[i].size, DPCI_ADD_MAPPING);
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}
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if (vga_args[i].rc) {
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XEN_PT_ERR(NULL, "VGA %s mapping failed! (rc: %i)\n",
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vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
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vga_args[i].rc);
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return vga_args[i].rc;
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}
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}
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return 0;
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}
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/*
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* unregister VGA resources for the domain with assigned gfx
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*/
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int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev)
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{
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int i = 0;
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int ret = 0;
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if (!is_igd_vga_passthrough(dev)) {
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return 0;
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}
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for (i = 0 ; i < ARRAY_SIZE(vga_args); i++) {
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if (vga_args[i].type == IORESOURCE_IO) {
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vga_args[i].rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
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vga_args[i].guest_base_addr,
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vga_args[i].machine_base_addr,
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vga_args[i].size, DPCI_REMOVE_MAPPING);
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} else {
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vga_args[i].rc = xc_domain_memory_mapping(xen_xc, xen_domid,
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vga_args[i].guest_base_addr,
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vga_args[i].machine_base_addr,
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vga_args[i].size, DPCI_REMOVE_MAPPING);
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}
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if (vga_args[i].rc) {
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XEN_PT_ERR(NULL, "VGA %s unmapping failed! (rc: %i)\n",
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vga_args[i].type == IORESOURCE_IO ? "ioport" : "memory",
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vga_args[i].rc);
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return vga_args[i].rc;
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}
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}
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if (igd_guest_opregion) {
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ret = xc_domain_memory_mapping(xen_xc, xen_domid,
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(unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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3,
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DPCI_REMOVE_MAPPING);
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if (ret) {
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return ret;
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}
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}
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return 0;
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}
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static void *get_vgabios(XenPCIPassthroughState *s, int *size,
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XenHostPCIDevice *dev)
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{
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return pci_assign_dev_load_option_rom(&s->dev, size,
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dev->domain, dev->bus,
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dev->dev, dev->func);
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}
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/* Refer to Seabios. */
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struct rom_header {
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uint16_t signature;
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uint8_t size;
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uint8_t initVector[4];
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uint8_t reserved[17];
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uint16_t pcioffset;
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uint16_t pnpoffset;
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} __attribute__((packed));
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struct pci_data {
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uint32_t signature;
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uint16_t vendor;
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uint16_t device;
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uint16_t vitaldata;
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uint16_t dlen;
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uint8_t drevision;
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uint8_t class_lo;
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uint16_t class_hi;
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uint16_t ilen;
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uint16_t irevision;
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uint8_t type;
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uint8_t indicator;
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uint16_t reserved;
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} __attribute__((packed));
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void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
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Error **errp)
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{
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unsigned char *bios = NULL;
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struct rom_header *rom;
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int bios_size;
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char *c = NULL;
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char checksum = 0;
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uint32_t len = 0;
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struct pci_data *pd = NULL;
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if (!is_igd_vga_passthrough(dev)) {
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error_setg(errp, "Need to enable igd-passthrough");
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return;
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}
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bios = get_vgabios(s, &bios_size, dev);
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if (!bios) {
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error_setg(errp, "VGA: Can't get VBIOS");
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return;
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}
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if (bios_size < sizeof(struct rom_header)) {
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error_setg(errp, "VGA: VBIOS image corrupt (too small)");
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return;
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}
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/* Currently we fixed this address as a primary. */
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rom = (struct rom_header *)bios;
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if (rom->pcioffset + sizeof(struct pci_data) > bios_size) {
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error_setg(errp, "VGA: VBIOS image corrupt (bad pcioffset field)");
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return;
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}
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pd = (void *)(bios + (unsigned char)rom->pcioffset);
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/* We may need to fixup Device Identification. */
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if (pd->device != s->real_device.device_id) {
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pd->device = s->real_device.device_id;
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len = rom->size * 512;
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if (len > bios_size) {
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error_setg(errp, "VGA: VBIOS image corrupt (bad size field)");
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return;
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}
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/* Then adjust the bios checksum */
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for (c = (char *)bios; c < ((char *)bios + len); c++) {
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checksum += *c;
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}
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if (checksum) {
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bios[len - 1] -= checksum;
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XEN_PT_LOG(&s->dev, "vga bios checksum is adjusted %x!\n",
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checksum);
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}
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}
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/* Currently we fixed this address as a primary for legacy BIOS. */
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cpu_physical_memory_write(0xc0000, bios, bios_size);
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}
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uint32_t igd_read_opregion(XenPCIPassthroughState *s)
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{
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uint32_t val = 0;
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if (!igd_guest_opregion) {
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return val;
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}
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val = igd_guest_opregion;
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XEN_PT_LOG(&s->dev, "Read opregion val=%x\n", val);
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return val;
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}
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#define XEN_PCI_INTEL_OPREGION_PAGES 0x3
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#define XEN_PCI_INTEL_OPREGION_ENABLE_ACCESSED 0x1
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void igd_write_opregion(XenPCIPassthroughState *s, uint32_t val)
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{
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int ret;
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if (igd_guest_opregion) {
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XEN_PT_LOG(&s->dev, "opregion register already been set, ignoring %x\n",
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val);
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return;
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}
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/* We just work with LE. */
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xen_host_pci_get_block(&s->real_device, XEN_PCI_INTEL_OPREGION,
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(uint8_t *)&igd_host_opregion, 4);
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igd_guest_opregion = (unsigned long)(val & ~XEN_PCI_INTEL_OPREGION_MASK)
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| (igd_host_opregion & XEN_PCI_INTEL_OPREGION_MASK);
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ret = xc_domain_iomem_permission(xen_xc, xen_domid,
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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XEN_PCI_INTEL_OPREGION_PAGES,
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XEN_PCI_INTEL_OPREGION_ENABLE_ACCESSED);
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if (ret) {
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XEN_PT_ERR(&s->dev, "[%d]:Can't enable to access IGD host opregion:"
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" 0x%lx.\n", ret,
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT)),
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igd_guest_opregion = 0;
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return;
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}
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ret = xc_domain_memory_mapping(xen_xc, xen_domid,
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(unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT),
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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XEN_PCI_INTEL_OPREGION_PAGES,
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DPCI_ADD_MAPPING);
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if (ret) {
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XEN_PT_ERR(&s->dev, "[%d]:Can't map IGD host opregion:0x%lx to"
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" guest opregion:0x%lx.\n", ret,
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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(unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT));
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igd_guest_opregion = 0;
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return;
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}
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XEN_PT_LOG(&s->dev, "Map OpRegion: 0x%lx -> 0x%lx\n",
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(unsigned long)(igd_host_opregion >> XC_PAGE_SHIFT),
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(unsigned long)(igd_guest_opregion >> XC_PAGE_SHIFT));
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}
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typedef struct {
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uint16_t gpu_device_id;
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uint16_t pch_device_id;
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uint8_t pch_revision_id;
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} IGDDeviceIDInfo;
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/*
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* In real world different GPU should have different PCH. But actually
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* the different PCH DIDs likely map to different PCH SKUs. We do the
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* same thing for the GPU. For PCH, the different SKUs are going to be
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* all the same silicon design and implementation, just different
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* features turn on and off with fuses. The SW interfaces should be
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* consistent across all SKUs in a given family (eg LPT). But just same
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* features may not be supported.
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*
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* Most of these different PCH features probably don't matter to the
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* Gfx driver, but obviously any difference in display port connections
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* will so it should be fine with any PCH in case of passthrough.
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*
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* So currently use one PCH version, 0x8c4e, to cover all HSW(Haswell)
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* scenarios, 0x9cc3 for BDW(Broadwell).
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*/
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static const IGDDeviceIDInfo igd_combo_id_infos[] = {
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/* HSW Classic */
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{0x0402, 0x8c4e, 0x04}, /* HSWGT1D, HSWD_w7 */
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{0x0406, 0x8c4e, 0x04}, /* HSWGT1M, HSWM_w7 */
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{0x0412, 0x8c4e, 0x04}, /* HSWGT2D, HSWD_w7 */
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{0x0416, 0x8c4e, 0x04}, /* HSWGT2M, HSWM_w7 */
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{0x041E, 0x8c4e, 0x04}, /* HSWGT15D, HSWD_w7 */
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/* HSW ULT */
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{0x0A06, 0x8c4e, 0x04}, /* HSWGT1UT, HSWM_w7 */
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{0x0A16, 0x8c4e, 0x04}, /* HSWGT2UT, HSWM_w7 */
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{0x0A26, 0x8c4e, 0x06}, /* HSWGT3UT, HSWM_w7 */
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{0x0A2E, 0x8c4e, 0x04}, /* HSWGT3UT28W, HSWM_w7 */
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{0x0A1E, 0x8c4e, 0x04}, /* HSWGT2UX, HSWM_w7 */
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{0x0A0E, 0x8c4e, 0x04}, /* HSWGT1ULX, HSWM_w7 */
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/* HSW CRW */
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{0x0D26, 0x8c4e, 0x04}, /* HSWGT3CW, HSWM_w7 */
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{0x0D22, 0x8c4e, 0x04}, /* HSWGT3CWDT, HSWD_w7 */
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/* HSW Server */
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{0x041A, 0x8c4e, 0x04}, /* HSWSVGT2, HSWD_w7 */
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/* HSW SRVR */
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{0x040A, 0x8c4e, 0x04}, /* HSWSVGT1, HSWD_w7 */
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/* BSW */
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{0x1606, 0x9cc3, 0x03}, /* BDWULTGT1, BDWM_w7 */
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{0x1616, 0x9cc3, 0x03}, /* BDWULTGT2, BDWM_w7 */
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{0x1626, 0x9cc3, 0x03}, /* BDWULTGT3, BDWM_w7 */
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{0x160E, 0x9cc3, 0x03}, /* BDWULXGT1, BDWM_w7 */
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{0x161E, 0x9cc3, 0x03}, /* BDWULXGT2, BDWM_w7 */
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{0x1602, 0x9cc3, 0x03}, /* BDWHALOGT1, BDWM_w7 */
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{0x1612, 0x9cc3, 0x03}, /* BDWHALOGT2, BDWM_w7 */
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{0x1622, 0x9cc3, 0x03}, /* BDWHALOGT3, BDWM_w7 */
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{0x162B, 0x9cc3, 0x03}, /* BDWHALO28W, BDWM_w7 */
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{0x162A, 0x9cc3, 0x03}, /* BDWGT3WRKS, BDWM_w7 */
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{0x162D, 0x9cc3, 0x03}, /* BDWGT3SRVR, BDWM_w7 */
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};
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static void isa_bridge_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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dc->desc = "ISA bridge faked to support IGD PT";
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->class_id = PCI_CLASS_BRIDGE_ISA;
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};
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static const TypeInfo isa_bridge_info = {
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.name = "igd-passthrough-isa-bridge",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = isa_bridge_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void pt_graphics_register_types(void)
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{
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type_register_static(&isa_bridge_info);
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}
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type_init(pt_graphics_register_types)
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void xen_igd_passthrough_isa_bridge_create(XenPCIPassthroughState *s,
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XenHostPCIDevice *dev)
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{
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PCIBus *bus = pci_get_bus(&s->dev);
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struct PCIDevice *bridge_dev;
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int i, num;
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const uint16_t gpu_dev_id = dev->device_id;
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uint16_t pch_dev_id = 0xffff;
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uint8_t pch_rev_id = 0;
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num = ARRAY_SIZE(igd_combo_id_infos);
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for (i = 0; i < num; i++) {
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if (gpu_dev_id == igd_combo_id_infos[i].gpu_device_id) {
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pch_dev_id = igd_combo_id_infos[i].pch_device_id;
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pch_rev_id = igd_combo_id_infos[i].pch_revision_id;
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}
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}
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if (pch_dev_id == 0xffff) {
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return;
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}
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/* Currently IGD drivers always need to access PCH by 1f.0. */
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bridge_dev = pci_create_simple(bus, PCI_DEVFN(0x1f, 0),
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"igd-passthrough-isa-bridge");
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/*
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* Note that vendor id is always PCI_VENDOR_ID_INTEL.
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*/
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if (!bridge_dev) {
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fprintf(stderr, "set igd-passthrough-isa-bridge failed!\n");
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return;
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}
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pci_config_set_device_id(bridge_dev->config, pch_dev_id);
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pci_config_set_revision(bridge_dev->config, pch_rev_id);
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}
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