- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
- Add '-d invalid_mem' logging option (Zoltan)
- Create QOM containers explicitly (Peter)
- Rename sysemu/ -> system/ (Philippe)
- Re-orderning of include/exec/ headers (Philippe)
Move a lot of declarations from these legacy mixed bag headers:
. "exec/cpu-all.h"
. "exec/cpu-common.h"
. "exec/cpu-defs.h"
. "exec/exec-all.h"
. "exec/translate-all"
to these more specific ones:
. "exec/page-protection.h"
. "exec/translation-block.h"
. "user/cpu_loop.h"
. "user/guest-host.h"
. "user/page-protection.h"
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Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging
Accel & Exec patch queue
- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
- Add '-d invalid_mem' logging option (Zoltan)
- Create QOM containers explicitly (Peter)
- Rename sysemu/ -> system/ (Philippe)
- Re-orderning of include/exec/ headers (Philippe)
Move a lot of declarations from these legacy mixed bag headers:
. "exec/cpu-all.h"
. "exec/cpu-common.h"
. "exec/cpu-defs.h"
. "exec/exec-all.h"
. "exec/translate-all"
to these more specific ones:
. "exec/page-protection.h"
. "exec/translation-block.h"
. "user/cpu_loop.h"
. "user/guest-host.h"
. "user/page-protection.h"
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 20 Dec 2024 11:45:20 EST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits)
util/qemu-timer: fix indentation
meson: Do not define CONFIG_DEVICES on user emulation
system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header
system/numa: Remove unnecessary 'exec/cpu-common.h' header
hw/xen: Remove unnecessary 'exec/cpu-common.h' header
target/mips: Drop left-over comment about Jazz machine
target/mips: Remove tswap() calls in semihosting uhi_fstat_cb()
target/xtensa: Remove tswap() calls in semihosting simcall() helper
accel/tcg: Un-inline translator_is_same_page()
accel/tcg: Include missing 'exec/translation-block.h' header
accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'
accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h'
qemu/coroutine: Include missing 'qemu/atomic.h' header
exec/translation-block: Include missing 'qemu/atomic.h' header
accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h'
exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined
target/sparc: Move sparc_restore_state_to_opc() to cpu.c
target/sparc: Uninline cpu_get_tb_cpu_state()
target/loongarch: Declare loongarch_cpu_dump_state() locally
user: Move various declarations out of 'exec/exec-all.h'
...
Conflicts:
hw/char/riscv_htif.c
hw/intc/riscv_aplic.c
target/s390x/cpu.c
Apply sysemu header path changes to not in the pull request.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
165 lines
4.2 KiB
C
165 lines
4.2 KiB
C
/*
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* KVM in-kernel IOPIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "monitor/monitor.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/ioapic_internal.h"
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#include "hw/intc/kvm_irqcount.h"
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#include "system/kvm.h"
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#include "kvm/kvm_i386.h"
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/* PC Utility function */
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void kvm_pc_setup_irq_routing(bool pci_enabled)
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{
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KVMState *s = kvm_state;
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int i;
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assert(kvm_has_gsi_routing());
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue;
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}
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
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}
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
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}
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if (pci_enabled) {
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for (i = 0; i < KVM_IOAPIC_NUM_PINS; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
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}
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}
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}
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kvm_irqchip_commit_routes(s);
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}
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typedef struct KVMIOAPICState KVMIOAPICState;
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struct KVMIOAPICState {
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IOAPICCommonState ioapic;
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uint32_t kvm_gsi_base;
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};
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static void kvm_ioapic_get(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(-ret));
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abort();
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}
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kioapic = &chip.chip.ioapic;
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s->id = kioapic->id;
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s->ioregsel = kioapic->ioregsel;
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s->irr = kioapic->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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s->ioredtbl[i] = kioapic->redirtbl[i].bits;
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}
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}
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static void kvm_ioapic_put(IOAPICCommonState *s)
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{
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struct kvm_irqchip chip;
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struct kvm_ioapic_state *kioapic;
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int ret, i;
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chip.chip_id = KVM_IRQCHIP_IOAPIC;
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kioapic = &chip.chip.ioapic;
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kioapic->id = s->id;
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kioapic->ioregsel = s->ioregsel;
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kioapic->base_address = s->busdev.mmio[0].addr;
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kioapic->irr = s->irr;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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kioapic->redirtbl[i].bits = s->ioredtbl[i];
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}
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ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip);
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if (ret < 0) {
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fprintf(stderr, "KVM_SET_IRQCHIP failed: %s\n", strerror(-ret));
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abort();
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}
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}
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static void kvm_ioapic_reset(DeviceState *dev)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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ioapic_reset_common(dev);
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kvm_ioapic_put(s);
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}
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static void kvm_ioapic_set_irq(void *opaque, int irq, int level)
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{
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KVMIOAPICState *s = opaque;
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IOAPICCommonState *common = IOAPIC_COMMON(s);
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int delivered;
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ioapic_stat_update_irq(common, irq, level);
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delivered = kvm_set_irq(kvm_state, s->kvm_gsi_base + irq, level);
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kvm_report_irq_delivered(delivered);
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}
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static void kvm_ioapic_realize(DeviceState *dev, Error **errp)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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memory_region_init_io(&s->io_memory, OBJECT(dev), NULL, NULL, "kvm-ioapic", 0x1000);
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/*
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* KVM ioapic only supports 0x11 now. This will only be used when
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* we want to dump ioapic version.
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*/
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s->version = 0x11;
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qdev_init_gpio_in(dev, kvm_ioapic_set_irq, IOAPIC_NUM_PINS);
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}
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static const Property kvm_ioapic_properties[] = {
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DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0),
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};
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static void kvm_ioapic_class_init(ObjectClass *klass, void *data)
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{
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IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->realize = kvm_ioapic_realize;
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k->pre_save = kvm_ioapic_get;
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k->post_load = kvm_ioapic_put;
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device_class_set_legacy_reset(dc, kvm_ioapic_reset);
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device_class_set_props(dc, kvm_ioapic_properties);
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}
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static const TypeInfo kvm_ioapic_info = {
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.name = TYPE_KVM_IOAPIC,
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.parent = TYPE_IOAPIC_COMMON,
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.instance_size = sizeof(KVMIOAPICState),
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.class_init = kvm_ioapic_class_init,
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};
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static void kvm_ioapic_register_types(void)
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{
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type_register_static(&kvm_ioapic_info);
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}
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type_init(kvm_ioapic_register_types)
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