Implement the ability to read and write characters to the usart using the serial port. The character transmission is based on the cmsdk-apb-uart implementation. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
		
			
				
	
	
		
			68 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			68 lines
		
	
	
		
			1.7 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
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 *
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 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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 *
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 *
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 * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
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 * by Alistair Francis.
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 * The reference used is the STMicroElectronics RM0351 Reference manual
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 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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 */
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#ifndef HW_STM32L4X5_USART_H
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#define HW_STM32L4X5_USART_H
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "qom/object.h"
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#define TYPE_STM32L4X5_USART_BASE "stm32l4x5-usart-base"
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#define TYPE_STM32L4X5_USART "stm32l4x5-usart"
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#define TYPE_STM32L4X5_UART "stm32l4x5-uart"
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#define TYPE_STM32L4X5_LPUART "stm32l4x5-lpuart"
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OBJECT_DECLARE_TYPE(Stm32l4x5UsartBaseState, Stm32l4x5UsartBaseClass,
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                    STM32L4X5_USART_BASE)
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typedef enum {
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    STM32L4x5_USART,
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    STM32L4x5_UART,
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    STM32L4x5_LPUART,
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} Stm32l4x5UsartType;
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struct Stm32l4x5UsartBaseState {
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    SysBusDevice parent_obj;
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    MemoryRegion mmio;
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    uint32_t cr1;
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    uint32_t cr2;
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    uint32_t cr3;
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    uint32_t brr;
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    uint32_t gtpr;
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    uint32_t rtor;
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    /* rqr is write-only */
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    uint32_t isr;
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    /* icr is a clear register */
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    uint32_t rdr;
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    uint32_t tdr;
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    Clock *clk;
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    CharBackend chr;
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    qemu_irq irq;
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    guint watch_tag;
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};
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struct Stm32l4x5UsartBaseClass {
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    SysBusDeviceClass parent_class;
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    Stm32l4x5UsartType type;
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};
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#endif /* HW_STM32L4X5_USART_H */
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