 8ef94f0bc9
			
		
	
	
		8ef94f0bc9
		
	
	
	
	
		
			
			Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-13-git-send-email-peter.maydell@linaro.org
		
			
				
	
	
		
			142 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			142 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * ARM GICv3 support - common bits of emulated and KVM kernel model
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|  *
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|  * Copyright (c) 2012 Linaro Limited
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|  * Copyright (c) 2015 Huawei.
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|  * Written by Peter Maydell
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|  * Extended to 64 cores by Shlomo Pongratz
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation, either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License along
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|  * with this program; if not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "hw/intc/arm_gicv3_common.h"
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| 
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| static void gicv3_pre_save(void *opaque)
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| {
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|     GICv3State *s = (GICv3State *)opaque;
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|     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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| 
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|     if (c->pre_save) {
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|         c->pre_save(s);
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|     }
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| }
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| 
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| static int gicv3_post_load(void *opaque, int version_id)
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| {
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|     GICv3State *s = (GICv3State *)opaque;
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|     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
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| 
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|     if (c->post_load) {
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|         c->post_load(s);
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|     }
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|     return 0;
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| }
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| 
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| static const VMStateDescription vmstate_gicv3 = {
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|     .name = "arm_gicv3",
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|     .unmigratable = 1,
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|     .pre_save = gicv3_pre_save,
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|     .post_load = gicv3_post_load,
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| };
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| 
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| void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
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|                               const MemoryRegionOps *ops)
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| {
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|     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
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|     int i;
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| 
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|     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
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|      * GPIO array layout is thus:
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|      *  [0..N-1] spi
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|      *  [N..N+31] PPIs for CPU 0
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|      *  [N+32..N+63] PPIs for CPU 1
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|      *   ...
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|      */
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|     i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
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|     qdev_init_gpio_in(DEVICE(s), handler, i);
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| 
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|     s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq));
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|     s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq));
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| 
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|     for (i = 0; i < s->num_cpu; i++) {
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|         sysbus_init_irq(sbd, &s->parent_irq[i]);
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|     }
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|     for (i = 0; i < s->num_cpu; i++) {
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|         sysbus_init_irq(sbd, &s->parent_fiq[i]);
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|     }
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| 
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|     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
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|                           "gicv3_dist", 0x10000);
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|     memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
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|                           "gicv3_redist", 0x20000 * s->num_cpu);
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| 
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|     sysbus_init_mmio(sbd, &s->iomem_dist);
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|     sysbus_init_mmio(sbd, &s->iomem_redist);
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| }
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| 
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| static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
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| {
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|     GICv3State *s = ARM_GICV3_COMMON(dev);
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| 
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|     /* revision property is actually reserved and currently used only in order
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|      * to keep the interface compatible with GICv2 code, avoiding extra
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|      * conditions. However, in future it could be used, for example, if we
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|      * implement GICv4.
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|      */
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|     if (s->revision != 3) {
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|         error_setg(errp, "unsupported GIC revision %d", s->revision);
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|         return;
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|     }
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| }
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| 
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| static void arm_gicv3_common_reset(DeviceState *dev)
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| {
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|     /* TODO */
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| }
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| 
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| static Property arm_gicv3_common_properties[] = {
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|     DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
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|     DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
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|     DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
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|     DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
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|     DEFINE_PROP_END_OF_LIST(),
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| };
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| 
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| static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
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| {
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|     DeviceClass *dc = DEVICE_CLASS(klass);
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| 
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|     dc->reset = arm_gicv3_common_reset;
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|     dc->realize = arm_gicv3_common_realize;
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|     dc->props = arm_gicv3_common_properties;
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|     dc->vmsd = &vmstate_gicv3;
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| }
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| 
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| static const TypeInfo arm_gicv3_common_type = {
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|     .name = TYPE_ARM_GICV3_COMMON,
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|     .parent = TYPE_SYS_BUS_DEVICE,
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|     .instance_size = sizeof(GICv3State),
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|     .class_size = sizeof(ARMGICv3CommonClass),
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|     .class_init = arm_gicv3_common_class_init,
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|     .abstract = true,
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| };
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| 
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| static void register_types(void)
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| {
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|     type_register_static(&arm_gicv3_common_type);
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| }
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| 
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| type_init(register_types)
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