 610f4e1764
			
		
	
	
		610f4e1764
		
	
	
	
	
		
			
			Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-40-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
		
			
				
	
	
		
			75 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			75 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| # A32 unconditional instructions
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| #
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| #  Copyright (c) 2019 Linaro, Ltd
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| #
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| # This library is free software; you can redistribute it and/or
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| # modify it under the terms of the GNU Lesser General Public
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| # License as published by the Free Software Foundation; either
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| # version 2 of the License, or (at your option) any later version.
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| #
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| # This library is distributed in the hope that it will be useful,
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| # but WITHOUT ANY WARRANTY; without even the implied warranty of
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| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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| # Lesser General Public License for more details.
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| #
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| # You should have received a copy of the GNU Lesser General Public
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| # License along with this library; if not, see <http://www.gnu.org/licenses/>.
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| 
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| #
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| # This file is processed by scripts/decodetree.py
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| #
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| # All insns that have 0xf in insn[31:28] are decoded here.
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| # All of those that have a COND field in insn[31:28] are in a32.decode
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| #
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| 
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| &empty           !extern
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| &i               !extern imm
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| &setend          E
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| 
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| # Branch with Link and Exchange
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| 
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| %imm24h          0:s24 24:1 !function=times_2
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| 
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| BLX_i            1111 101 . ........................          &i imm=%imm24h
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| 
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| # System Instructions
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| 
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| &rfe             rn w pu
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| &srs             mode w pu
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| &cps             mode imod M A I F
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| 
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| RFE              1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000   &rfe
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| SRS              1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5  &srs
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| CPS              1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \
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|                  &cps
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| 
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| # Clear-Exclusive, Barriers
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| 
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| # QEMU does not require the option field for the barriers.
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| CLREX            1111 0101 0111 1111 1111 0000 0001 1111
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| DSB              1111 0101 0111 1111 1111 0000 0100 ----
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| DMB              1111 0101 0111 1111 1111 0000 0101 ----
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| ISB              1111 0101 0111 1111 1111 0000 0110 ----
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| SB               1111 0101 0111 1111 1111 0000 0111 0000
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| 
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| # Set Endianness
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| SETEND           1111 0001 0000 0001 0000 00 E:1 0 0000 0000  &setend
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| 
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| # Preload instructions
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| 
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| PLD              1111 0101 -101 ---- 1111 ---- ---- ----    # (imm, lit) 5te
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| PLDW             1111 0101 -001 ---- 1111 ---- ---- ----    # (imm, lit) 7mp
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| PLI              1111 0100 -101 ---- 1111 ---- ---- ----    # (imm, lit) 7
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| 
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| PLD              1111 0111 -101 ---- 1111 ----- -- 0 ----   # (register) 5te
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| PLDW             1111 0111 -001 ---- 1111 ----- -- 0 ----   # (register) 7mp
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| PLI              1111 0110 -101 ---- 1111 ----- -- 0 ----   # (register) 7
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| 
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| # Unallocated memory hints
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| #
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| # Since these are v7MP nops, and PLDW is v7MP and implemented as nop,
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| # (ab)use the PLDW helper.
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| 
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| PLDW             1111 0100 -001 ---- ---- ---- ---- ----
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| PLDW             1111 0110 -001 ---- ---- ---- ---0 ----
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