Bin Meng b93777e1b4 target/riscv: Generate the GDB XML file for CSR registers dynamically ...

At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:

- The XML does not specify the "regnum" field of a CSR entry, hence
  consecutive numbers are used by the remote GDB client to access
  CSRs. In QEMU we have to maintain a map table to convert the GDB
  number to the hardware number which is error prone.
- The XML contains some CSRs that QEMU does not implement at all,
  which causes an "E14" response sent to remote GDB client.

Change to generate the CSR register list dynamically, based on the
availability presented in the CSR function table. This new approach
will reflect a correct list of CSRs that QEMU actually implements.

[1] https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-01-16 10:57:21 -08:00

..

insn_trans

target/riscv: Split the Hypervisor execute load helpers

2020-11-09 15:09:00 -08:00

cpu_bits.h

target/riscv: csr: Remove compile time XLEN checks

2020-12-17 21:56:44 -08:00

cpu_helper.c

target/riscv: cpu_helper: Remove compile time XLEN checks

2020-12-17 21:56:44 -08:00

cpu_user.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

cpu-param.h

target/riscv: Add a virtualised MMU Mode

2020-11-09 15:08:45 -08:00

cpu.c

target/riscv: Generate the GDB XML file for CSR registers dynamically

2021-01-16 10:57:21 -08:00

cpu.h

target/riscv: Generate the GDB XML file for CSR registers dynamically

2021-01-16 10:57:21 -08:00

csr.c

target/riscv: Add CSR name in the CSR function table

2021-01-16 10:57:21 -08:00

fpu_helper.c

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

gdbstub.c

target/riscv: Generate the GDB XML file for CSR registers dynamically

2021-01-16 10:57:21 -08:00

helper.h

target/riscv: fpu_helper: Match function defs in HELPER macros

2020-12-17 21:56:44 -08:00

insn16-32.decode

target/riscv: Split RVC32 and RVC64 insns into separate files

2019-05-24 12:09:22 -07:00

insn16-64.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn16.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn32-64.decode

target/riscv: Allow generating hlv/hlvx/hsv instructions

2020-08-25 09:11:35 -07:00

insn32.decode

target/riscv: Allow generating hlv/hlvx/hsv instructions

2020-08-25 09:11:35 -07:00

instmap.h

target/riscv: progressively load the instruction during decode

2020-02-25 20:20:23 +00:00

internals.h

target/riscv: Add basic vmstate description of CPU

2020-11-03 07:17:23 -08:00

machine.c

target/riscv: Add V extension state description

2020-11-03 07:17:23 -08:00

meson.build

target/riscv: Add basic vmstate description of CPU

2020-11-03 07:17:23 -08:00

monitor.c

hmp: Pass monitor to mon_get_cpu_env()

2020-11-13 12:45:51 +00:00

op_helper.c

target/riscv/pmp: Raise exception if no PMP entry is configured

2021-01-16 10:57:21 -08:00

pmp.c

target/riscv/pmp: Raise exception if no PMP entry is configured

2021-01-16 10:57:21 -08:00

pmp.h

target/riscv/pmp: Raise exception if no PMP entry is configured

2021-01-16 10:57:21 -08:00

trace-events

trace-events: Fix attribution of trace points to source

2020-09-09 17:17:58 +01:00

trace.h

trace: switch position of headers to what Meson requires

2020-08-21 06:18:24 -04:00

translate.c

target/riscv: Remove the hyp load and store functions

2020-11-09 15:08:57 -08:00

vector_helper.c

softfloat: Implement the full set of comparisons for float16

2020-08-28 10:48:07 -07:00