2cf91b9ae6
Fixes: e34136d93059 "linux-user/ppc: Add vdso" Fixes: 86f04735ac20 "linux-user: Fix brk() to release pages" Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
240 lines
6.5 KiB
ArmAsm
240 lines
6.5 KiB
ArmAsm
/*
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* PowerPC linux replacement vdso.
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*
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* Copyright 2023 Linaro, Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#ifndef _ARCH_PPC64
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# define TARGET_ABI32
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#endif
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#include "vdso-asmoffset.h"
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.text
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.macro endf name
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.globl \name
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.size \name, .-\name
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/* For PPC64, functions have special linkage; we export pointers. */
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#ifndef _ARCH_PPC64
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.type \name, @function
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#endif
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.endm
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.macro raw_syscall nr
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addi 0, 0, \nr
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sc
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.endm
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.macro vdso_syscall name, nr
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\name:
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raw_syscall \nr
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blr
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endf \name
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.endm
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.cfi_startproc
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vdso_syscall __kernel_gettimeofday, __NR_gettimeofday
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vdso_syscall __kernel_clock_gettime, __NR_clock_gettime
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vdso_syscall __kernel_clock_getres, __NR_clock_getres
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vdso_syscall __kernel_getcpu, __NR_getcpu
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vdso_syscall __kernel_time, __NR_time
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#ifdef __NR_clock_gettime64
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vdso_syscall __kernel_clock_gettime64, __NR_clock_gettime64
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#endif
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__kernel_sync_dicache:
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/* qemu does not need to flush caches */
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blr
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endf __kernel_sync_dicache
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.cfi_endproc
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/*
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* TODO: __kernel_get_tbfreq
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* This is probably a constant for QEMU.
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*/
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/*
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* Start the unwind info at least one instruction before the signal
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* trampoline, because the unwinder will assume we are returning
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* after a call site.
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*/
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.cfi_startproc simple
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.cfi_signal_frame
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#ifdef _ARCH_PPC64
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# define __kernel_sigtramp_rt __kernel_sigtramp_rt64
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# define sizeof_reg 8
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#else
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# define __kernel_sigtramp_rt __kernel_sigtramp_rt32
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# define sizeof_reg 4
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#endif
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#define sizeof_freg 8
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#define sizeof_vreg 16
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.cfi_def_cfa 1, SIGNAL_FRAMESIZE + offsetof_rt_sigframe_mcontext
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/* Return address */
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.cfi_return_column 67
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.cfi_offset 67, 32 * sizeof_reg /* nip */
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/* Integer registers */
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.cfi_offset 0, 0 * sizeof_reg
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.cfi_offset 1, 1 * sizeof_reg
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.cfi_offset 2, 2 * sizeof_reg
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.cfi_offset 3, 3 * sizeof_reg
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.cfi_offset 4, 4 * sizeof_reg
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.cfi_offset 5, 5 * sizeof_reg
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.cfi_offset 6, 6 * sizeof_reg
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.cfi_offset 7, 7 * sizeof_reg
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.cfi_offset 8, 8 * sizeof_reg
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.cfi_offset 9, 9 * sizeof_reg
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.cfi_offset 10, 10 * sizeof_reg
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.cfi_offset 11, 11 * sizeof_reg
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.cfi_offset 12, 12 * sizeof_reg
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.cfi_offset 13, 13 * sizeof_reg
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.cfi_offset 14, 14 * sizeof_reg
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.cfi_offset 15, 15 * sizeof_reg
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.cfi_offset 16, 16 * sizeof_reg
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.cfi_offset 17, 17 * sizeof_reg
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.cfi_offset 18, 18 * sizeof_reg
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.cfi_offset 19, 19 * sizeof_reg
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.cfi_offset 20, 20 * sizeof_reg
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.cfi_offset 21, 21 * sizeof_reg
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.cfi_offset 22, 22 * sizeof_reg
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.cfi_offset 23, 23 * sizeof_reg
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.cfi_offset 24, 24 * sizeof_reg
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.cfi_offset 25, 25 * sizeof_reg
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.cfi_offset 26, 26 * sizeof_reg
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.cfi_offset 27, 27 * sizeof_reg
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.cfi_offset 28, 28 * sizeof_reg
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.cfi_offset 29, 29 * sizeof_reg
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.cfi_offset 30, 30 * sizeof_reg
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.cfi_offset 31, 31 * sizeof_reg
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.cfi_offset 65, 36 * sizeof_reg /* lr */
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.cfi_offset 70, 38 * sizeof_reg /* ccr */
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/* Floating point registers */
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.cfi_offset 32, offsetof_mcontext_fregs
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.cfi_offset 33, offsetof_mcontext_fregs + 1 * sizeof_freg
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.cfi_offset 34, offsetof_mcontext_fregs + 2 * sizeof_freg
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.cfi_offset 35, offsetof_mcontext_fregs + 3 * sizeof_freg
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.cfi_offset 36, offsetof_mcontext_fregs + 4 * sizeof_freg
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.cfi_offset 37, offsetof_mcontext_fregs + 5 * sizeof_freg
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.cfi_offset 38, offsetof_mcontext_fregs + 6 * sizeof_freg
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.cfi_offset 39, offsetof_mcontext_fregs + 7 * sizeof_freg
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.cfi_offset 40, offsetof_mcontext_fregs + 8 * sizeof_freg
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.cfi_offset 41, offsetof_mcontext_fregs + 9 * sizeof_freg
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.cfi_offset 42, offsetof_mcontext_fregs + 10 * sizeof_freg
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.cfi_offset 43, offsetof_mcontext_fregs + 11 * sizeof_freg
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.cfi_offset 44, offsetof_mcontext_fregs + 12 * sizeof_freg
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.cfi_offset 45, offsetof_mcontext_fregs + 13 * sizeof_freg
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.cfi_offset 46, offsetof_mcontext_fregs + 14 * sizeof_freg
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.cfi_offset 47, offsetof_mcontext_fregs + 15 * sizeof_freg
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.cfi_offset 48, offsetof_mcontext_fregs + 16 * sizeof_freg
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.cfi_offset 49, offsetof_mcontext_fregs + 17 * sizeof_freg
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.cfi_offset 50, offsetof_mcontext_fregs + 18 * sizeof_freg
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.cfi_offset 51, offsetof_mcontext_fregs + 19 * sizeof_freg
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.cfi_offset 52, offsetof_mcontext_fregs + 20 * sizeof_freg
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.cfi_offset 53, offsetof_mcontext_fregs + 21 * sizeof_freg
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.cfi_offset 54, offsetof_mcontext_fregs + 22 * sizeof_freg
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.cfi_offset 55, offsetof_mcontext_fregs + 23 * sizeof_freg
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.cfi_offset 56, offsetof_mcontext_fregs + 24 * sizeof_freg
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.cfi_offset 57, offsetof_mcontext_fregs + 25 * sizeof_freg
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.cfi_offset 58, offsetof_mcontext_fregs + 26 * sizeof_freg
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.cfi_offset 59, offsetof_mcontext_fregs + 27 * sizeof_freg
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.cfi_offset 60, offsetof_mcontext_fregs + 28 * sizeof_freg
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.cfi_offset 61, offsetof_mcontext_fregs + 29 * sizeof_freg
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.cfi_offset 62, offsetof_mcontext_fregs + 30 * sizeof_freg
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.cfi_offset 63, offsetof_mcontext_fregs + 31 * sizeof_freg
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/*
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* Unlike the kernel, unconditionally represent the Altivec/VSX regs.
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* The space within the stack frame is always available, and most of
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* our supported processors have them enabled. The only complication
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* for PPC64 is the misalignment, so that we have to use indirection.
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*/
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.macro save_vreg_ofs reg, ofs
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#ifdef _ARCH_PPC64
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/*
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* vreg = *(cfa + offsetof(v_regs)) + ofs
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*
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* The CFA is input to the expression on the stack, so:
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* DW_CFA_expression reg, length (7),
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* DW_OP_plus_uconst (0x23), vreg_ptr, DW_OP_deref (0x06),
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* DW_OP_plus_uconst (0x23), ofs
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*/
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.cfi_escape 0x10, 77 + \reg, 7, 0x23, (offsetof_mcontext_vregs_ptr & 0x7f) + 0x80, offsetof_mcontext_vregs_ptr >> 7, 0x06, 0x23, (\ofs & 0x7f) | 0x80, \ofs >> 7
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#else
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.cfi_offset 77 + \reg, offsetof_mcontext_vregs + \ofs
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#endif
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.endm
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.macro save_vreg reg
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save_vreg_ofs \reg, (\reg * sizeof_vreg)
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.endm
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save_vreg 0
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save_vreg 1
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save_vreg 2
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save_vreg 3
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save_vreg 4
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save_vreg 5
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save_vreg 6
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save_vreg 7
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save_vreg 8
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save_vreg 9
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save_vreg 10
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save_vreg 11
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save_vreg 12
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save_vreg 13
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save_vreg 14
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save_vreg 15
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save_vreg 16
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save_vreg 17
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save_vreg 18
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save_vreg 19
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save_vreg 20
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save_vreg 21
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save_vreg 22
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save_vreg 23
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save_vreg 24
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save_vreg 25
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save_vreg 26
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save_vreg 27
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save_vreg 28
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save_vreg 29
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save_vreg 30
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save_vreg 31
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save_vreg 32
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save_vreg_ofs 33, (32 * sizeof_vreg + 12)
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nop
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__kernel_sigtramp_rt:
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raw_syscall __NR_rt_sigreturn
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endf __kernel_sigtramp_rt
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#ifndef _ARCH_PPC64
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/*
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* The non-rt sigreturn has the same layout at a different offset.
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* Move the CFA and leave all the other descriptions the same.
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*/
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.cfi_def_cfa 1, SIGNAL_FRAMESIZE + offsetof_sigframe_mcontext
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nop
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__kernel_sigtramp32:
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raw_syscall __NR_sigreturn
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endf __kernel_sigtramp32
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#endif
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.cfi_endproc
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