1f1a7b2269
According to 7.2.2 in [1] bit 27 is the last bit that can be part of the
bus number, this makes the ECAM max size equal to '1 << 28'. This patch
restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was
changed in commit 58d5b22bbd5 ("ppc4xx: Add device models found in PPC440
core SoCs")).
[1] PCI Express® Base Specification Revision 5.0 Version 1.0
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
82 lines
2.8 KiB
C
82 lines
2.8 KiB
C
/*
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* pcie_host.h
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*
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* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PCIE_HOST_H
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#define PCIE_HOST_H
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#include "hw/pci/pci_host.h"
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#include "exec/memory.h"
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#include "qom/object.h"
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#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIExpressHost, PCIE_HOST_BRIDGE)
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#define PCIE_HOST_MCFG_BASE "MCFG"
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#define PCIE_HOST_MCFG_SIZE "mcfg_size"
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/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
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#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
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struct PCIExpressHost {
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PCIHostState pci;
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/* express part */
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/* base address where MMCONFIG area is mapped. */
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hwaddr base_addr;
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/* the size of MMCONFIG area. It's host bridge dependent */
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hwaddr size;
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/* MMCONFIG mmio area */
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MemoryRegion mmio;
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};
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void pcie_host_mmcfg_unmap(PCIExpressHost *e);
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void pcie_host_mmcfg_init(PCIExpressHost *e, uint32_t size);
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void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, uint32_t size);
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void pcie_host_mmcfg_update(PCIExpressHost *e,
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int enable,
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hwaddr addr,
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uint32_t size);
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/*
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* PCI express ECAM (Enhanced Configuration Address Mapping) format.
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* AKA mmcfg address
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* bit 20 - 27: bus number
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* bit 15 - 19: device number
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* bit 12 - 14: function number
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* bit 0 - 11: offset in configuration space of a given device
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*/
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
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#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
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#define PCIE_MMCFG_BUS_BIT 20
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#define PCIE_MMCFG_BUS_MASK 0xff
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#define PCIE_MMCFG_DEVFN_BIT 12
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#define PCIE_MMCFG_DEVFN_MASK 0xff
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#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
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#define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
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PCIE_MMCFG_BUS_MASK)
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#define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
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PCIE_MMCFG_DEVFN_MASK)
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#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
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#endif /* PCIE_HOST_H */
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