be1765f398
The pci_ide_create_devs() function takes a hd_table parameter but all callers just pass what ide_drive_get() returns so we can do it locally simplifying callers and removing hd_table parameter. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: e9713fdded4d212fa68ed03b844e531934226a6f.1584457537.git.balaton@eik.bme.hu Signed-off-by: John Snow <jsnow@redhat.com>
74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* QEMU PIIX South Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2018 Hervé Poussineau
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef HW_SOUTHBRIDGE_PIIX_H
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#define HW_SOUTHBRIDGE_PIIX_H
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#include "hw/pci/pci.h"
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#define TYPE_PIIX4_PM "PIIX4_PM"
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I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
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qemu_irq sci_irq, qemu_irq smi_irq,
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int smm_enabled, DeviceState **piix4_pm);
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/* PIRQRC[A:D]: PIRQx Route Control Registers */
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#define PIIX_PIRQCA 0x60
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#define PIIX_PIRQCB 0x61
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#define PIIX_PIRQCC 0x62
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#define PIIX_PIRQCD 0x63
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/*
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* Reset Control Register: PCI-accessible ISA-Compatible Register at address
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* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
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*/
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#define PIIX_RCR_IOPORT 0xcf9
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#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
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typedef struct PIIXState {
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PCIDevice dev;
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/*
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* bitmap to track pic levels.
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* The pic level is the logical OR of all the PCI irqs mapped to it
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
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#error "unable to encode pic state in 64bit in pic_levels."
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#endif
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uint64_t pic_levels;
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qemu_irq *pic;
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
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/* Reset Control Register contents */
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uint8_t rcr;
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/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
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MemoryRegion rcr_mem;
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} PIIX3State;
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extern PCIDevice *piix4_dev;
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PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
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DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
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#endif
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