fe0fe4735e
This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
69 lines
1.6 KiB
C
69 lines
1.6 KiB
C
/*
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* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
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*
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* Copyright (c) 2020 Western Digital
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_OPENTITAN_H
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#define HW_OPENTITAN_H
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#include "hw/riscv/riscv_hart.h"
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#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
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#define RISCV_IBEX_SOC(obj) \
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OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC)
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typedef struct LowRISCIbexSoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState cpus;
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MemoryRegion flash_mem;
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MemoryRegion rom;
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} LowRISCIbexSoCState;
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typedef struct OpenTitanState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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LowRISCIbexSoCState soc;
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} OpenTitanState;
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enum {
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IBEX_ROM,
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IBEX_RAM,
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IBEX_FLASH,
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IBEX_UART,
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IBEX_GPIO,
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IBEX_SPI,
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IBEX_FLASH_CTRL,
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IBEX_RV_TIMER,
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IBEX_AES,
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IBEX_HMAC,
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IBEX_PLIC,
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IBEX_PWRMGR,
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IBEX_RSTMGR,
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IBEX_CLKMGR,
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IBEX_PINMUX,
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IBEX_ALERT_HANDLER,
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IBEX_NMI_GEN,
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IBEX_USBDEV,
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IBEX_PADCTRL,
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};
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#endif
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