99f575edcc
Add OpenRISC timer support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/*
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* QEMU OpenRISC timer support
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "hw.h"
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#include "qemu-timer.h"
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#define TIMER_FREQ (20 * 1000 * 1000) /* 20MHz */
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/* The time when TTCR changes */
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static uint64_t last_clk;
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static int is_counting;
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void cpu_openrisc_count_update(OpenRISCCPU *cpu)
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{
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uint64_t now, next;
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uint32_t wait;
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now = qemu_get_clock_ns(vm_clock);
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if (!is_counting) {
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qemu_del_timer(cpu->env.timer);
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last_clk = now;
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return;
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}
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cpu->env.ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ,
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get_ticks_per_sec());
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last_clk = now;
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if ((cpu->env.ttmr & TTMR_TP) <= (cpu->env.ttcr & TTMR_TP)) {
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wait = TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1;
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wait += cpu->env.ttmr & TTMR_TP;
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} else {
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wait = (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP);
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}
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next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
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qemu_mod_timer(cpu->env.timer, next);
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}
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void cpu_openrisc_count_start(OpenRISCCPU *cpu)
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{
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is_counting = 1;
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cpu_openrisc_count_update(cpu);
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}
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void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
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{
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is_counting = 0;
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cpu_openrisc_count_update(cpu);
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}
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static void openrisc_timer_cb(void *opaque)
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{
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OpenRISCCPU *cpu = opaque;
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if ((cpu->env.ttmr & TTMR_IE) &&
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qemu_timer_expired(cpu->env.timer, qemu_get_clock_ns(vm_clock))) {
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cpu->env.ttmr |= TTMR_IP;
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cpu->env.interrupt_request |= CPU_INTERRUPT_TIMER;
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}
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switch (cpu->env.ttmr & TTMR_M) {
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case TIMER_NONE:
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break;
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case TIMER_INTR:
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cpu->env.ttcr = 0;
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cpu_openrisc_count_start(cpu);
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break;
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case TIMER_SHOT:
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cpu_openrisc_count_stop(cpu);
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break;
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case TIMER_CONT:
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cpu_openrisc_count_start(cpu);
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break;
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}
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}
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void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
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{
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cpu->env.timer = qemu_new_timer_ns(vm_clock, &openrisc_timer_cb, cpu);
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cpu->env.ttmr = 0x00000000;
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cpu->env.ttcr = 0x00000000;
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}
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