Paolo Bonzini a5505f6b5b target/i386: tcg: fix loading of registers from 16-bit TSS ...

According to the manual, the high 16-bit of the registers are preserved
when switching to a 16-bit task.  Implement this in switch_tss_ra.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2021-06-04 13:47:08 +02:00

..

alpha

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

arm

target/arm: Enable BFloat16 extensions

2021-06-03 16:43:26 +01:00

avr

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

cris

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

hexagon

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

hppa

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

i386

target/i386: tcg: fix loading of registers from 16-bit TSS

2021-06-04 13:47:08 +02:00

m68k

softfloat: Introduce Floatx80RoundPrec

2021-06-03 14:04:02 -07:00

microblaze

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

mips

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

nios2

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

openrisc

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

ppc

target/ppc: fix single-step exception regression

2021-06-03 18:10:31 +10:00

riscv

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

rx

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

s390x

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

sh4

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

sparc

docs: fix references to docs/devel/tracing.rst

2021-06-02 06:51:09 +02:00

tricore

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

xtensa

hw/core: Constify TCGCPUOps

2021-05-26 15:33:59 -07:00

meson.build

Drop the deprecated unicore32 target

2021-05-12 18:20:52 +02:00