828d651c58
A device shouldn't access its parent object which is QOM internal. Instead it should use type cast for this purporse. This patch fixes this issue for all NPCM7XX Devices. Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210108190945.949196-7-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
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* Nuvoton NPCM7xx Memory Controller stub
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/mem/npcm7xx_mc.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#define NPCM7XX_MC_REGS_SIZE (4 * KiB)
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static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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/*
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* If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory
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* controller has already been initialized and will skip DDR training.
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*/
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if (addr == 0) {
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return 0x100;
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}
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qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
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return 0;
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}
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static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
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}
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static const MemoryRegionOps npcm7xx_mc_ops = {
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.read = npcm7xx_mc_read,
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.write = npcm7xx_mc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
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{
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NPCM7xxMCState *s = NPCM7XX_MC(dev);
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memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
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NPCM7XX_MC_REGS_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
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}
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static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "NPCM7xx Memory Controller stub";
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dc->realize = npcm7xx_mc_realize;
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}
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static const TypeInfo npcm7xx_mc_types[] = {
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{
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.name = TYPE_NPCM7XX_MC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxMCState),
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.class_init = npcm7xx_mc_class_init,
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},
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};
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DEFINE_TYPES(npcm7xx_mc_types);
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