858ab7140d
Musca boards use the embedded subsystems (SSE) tied to a specific
Cortex core. Our models only use the Cortex-M33.
Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.
Remove the now unused MachineClass::default_cpu_type field.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
676 lines
24 KiB
C
676 lines
24 KiB
C
/*
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* Arm Musca-B1 test chip board emulation
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*
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* Copyright (c) 2019 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* The Musca boards are a reference implementation of a system using
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* the SSE-200 subsystem for embedded:
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* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board
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* https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board
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* We model the A and B1 variants of this board, as described in the TRMs:
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* https://developer.arm.com/documentation/101107/latest/
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* https://developer.arm.com/documentation/101312/latest/
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/boot.h"
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#include "hw/arm/armsse.h"
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#include "hw/boards.h"
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#include "hw/char/pl011.h"
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#include "hw/core/split-irq.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/misc/tz-ppc.h"
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#include "hw/misc/unimp.h"
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#include "hw/rtc/pl031.h"
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#include "hw/qdev-clock.h"
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#include "qom/object.h"
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#define MUSCA_NUMIRQ_MAX 96
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#define MUSCA_PPC_MAX 3
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#define MUSCA_MPC_MAX 5
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typedef struct MPCInfo MPCInfo;
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typedef enum MuscaType {
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MUSCA_A,
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MUSCA_B1,
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} MuscaType;
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struct MuscaMachineClass {
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MachineClass parent;
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MuscaType type;
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uint32_t init_svtor;
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int sram_addr_width;
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int num_irqs;
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const MPCInfo *mpc_info;
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int num_mpcs;
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};
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struct MuscaMachineState {
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MachineState parent;
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ARMSSE sse;
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/* RAM and flash */
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MemoryRegion ram[MUSCA_MPC_MAX];
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SplitIRQ cpu_irq_splitter[MUSCA_NUMIRQ_MAX];
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SplitIRQ sec_resp_splitter;
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TZPPC ppc[MUSCA_PPC_MAX];
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MemoryRegion container;
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UnimplementedDeviceState eflash[2];
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UnimplementedDeviceState qspi;
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TZMPC mpc[MUSCA_MPC_MAX];
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UnimplementedDeviceState mhu[2];
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UnimplementedDeviceState pwm[3];
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UnimplementedDeviceState i2s;
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PL011State uart[2];
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UnimplementedDeviceState i2c[2];
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UnimplementedDeviceState spi;
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UnimplementedDeviceState scc;
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UnimplementedDeviceState timer;
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PL031State rtc;
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UnimplementedDeviceState pvt;
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UnimplementedDeviceState sdio;
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UnimplementedDeviceState gpio;
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UnimplementedDeviceState cryptoisland;
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Clock *sysclk;
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Clock *s32kclk;
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};
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#define TYPE_MUSCA_MACHINE "musca"
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#define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")
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#define TYPE_MUSCA_B1_MACHINE MACHINE_TYPE_NAME("musca-b1")
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OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
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/*
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* Main SYSCLK frequency in Hz
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* TODO this should really be different for the two cores, but we
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* don't model that in our SSE-200 model yet.
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*/
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#define SYSCLK_FRQ 40000000
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/* Slow 32Khz S32KCLK frequency in Hz */
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#define S32KCLK_FRQ (32 * 1000)
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static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
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{
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/* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
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assert(irqno < MUSCA_NUMIRQ_MAX);
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return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
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}
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/*
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* Most of the devices in the Musca board sit behind Peripheral Protection
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* Controllers. These data structures define the layout of which devices
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* sit behind which PPCs.
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* The devfn for each port is a function which creates, configures
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* and initializes the device, returning the MemoryRegion which
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* needs to be plugged into the downstream end of the PPC port.
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*/
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typedef MemoryRegion *MakeDevFn(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size);
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typedef struct PPCPortInfo {
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const char *name;
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MakeDevFn *devfn;
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void *opaque;
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hwaddr addr;
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hwaddr size;
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} PPCPortInfo;
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typedef struct PPCInfo {
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const char *name;
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PPCPortInfo ports[TZ_NUM_PORTS];
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} PPCInfo;
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static MemoryRegion *make_unimp_dev(MuscaMachineState *mms,
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void *opaque, const char *name, hwaddr size)
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{
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/*
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* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE,
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* and return a pointer to its MemoryRegion.
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*/
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UnimplementedDeviceState *uds = opaque;
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object_initialize_child(OBJECT(mms), name, uds, TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(DEVICE(uds), "name", name);
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qdev_prop_set_uint64(DEVICE(uds), "size", size);
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sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
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}
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typedef enum MPCInfoType {
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MPC_RAM,
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MPC_ROM,
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MPC_CRYPTOISLAND,
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} MPCInfoType;
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struct MPCInfo {
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const char *name;
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hwaddr addr;
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hwaddr size;
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MPCInfoType type;
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};
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/* Order of the MPCs here must match the order of the bits in SECMPCINTSTATUS */
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static const MPCInfo a_mpc_info[] = { {
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.name = "qspi",
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.type = MPC_ROM,
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.addr = 0x00200000,
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.size = 0x00800000,
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}, {
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.name = "sram",
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.type = MPC_RAM,
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.addr = 0x00000000,
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.size = 0x00200000,
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}
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};
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static const MPCInfo b1_mpc_info[] = { {
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.name = "qspi",
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.type = MPC_ROM,
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.addr = 0x00000000,
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.size = 0x02000000,
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}, {
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.name = "sram",
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.type = MPC_RAM,
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.addr = 0x0a400000,
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.size = 0x00080000,
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}, {
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.name = "eflash0",
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.type = MPC_ROM,
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.addr = 0x0a000000,
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.size = 0x00200000,
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}, {
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.name = "eflash1",
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.type = MPC_ROM,
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.addr = 0x0a200000,
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.size = 0x00200000,
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}, {
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.name = "cryptoisland",
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.type = MPC_CRYPTOISLAND,
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.addr = 0x0a000000,
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.size = 0x00200000,
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}
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};
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static MemoryRegion *make_mpc(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size)
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{
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/*
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* Create an MPC and the RAM or flash behind it.
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* MPC 0: eFlash 0
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* MPC 1: eFlash 1
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* MPC 2: SRAM
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* MPC 3: QSPI flash
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* MPC 4: CryptoIsland
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* For now we implement the flash regions as ROM (ie not programmable)
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* (with their control interface memory regions being unimplemented
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* stubs behind the PPCs).
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* The whole CryptoIsland region behind its MPC is an unimplemented stub.
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*/
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MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
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TZMPC *mpc = opaque;
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int i = mpc - &mms->mpc[0];
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MemoryRegion *downstream;
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MemoryRegion *upstream;
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UnimplementedDeviceState *uds;
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char *mpcname;
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const MPCInfo *mpcinfo = mmc->mpc_info;
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mpcname = g_strdup_printf("%s-mpc", mpcinfo[i].name);
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switch (mpcinfo[i].type) {
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case MPC_ROM:
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downstream = &mms->ram[i];
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memory_region_init_rom(downstream, NULL, mpcinfo[i].name,
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mpcinfo[i].size, &error_fatal);
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break;
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case MPC_RAM:
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downstream = &mms->ram[i];
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memory_region_init_ram(downstream, NULL, mpcinfo[i].name,
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mpcinfo[i].size, &error_fatal);
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break;
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case MPC_CRYPTOISLAND:
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/* We don't implement the CryptoIsland yet */
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uds = &mms->cryptoisland;
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object_initialize_child(OBJECT(mms), name, uds,
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TYPE_UNIMPLEMENTED_DEVICE);
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qdev_prop_set_string(DEVICE(uds), "name", mpcinfo[i].name);
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qdev_prop_set_uint64(DEVICE(uds), "size", mpcinfo[i].size);
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sysbus_realize(SYS_BUS_DEVICE(uds), &error_fatal);
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downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0);
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break;
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default:
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g_assert_not_reached();
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}
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object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC);
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object_property_set_link(OBJECT(mpc), "downstream", OBJECT(downstream),
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&error_fatal);
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sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal);
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/* Map the upstream end of the MPC into system memory */
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upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1);
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memory_region_add_subregion(get_system_memory(), mpcinfo[i].addr, upstream);
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/* and connect its interrupt to the SSE-200 */
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qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0,
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qdev_get_gpio_in_named(DEVICE(&mms->sse),
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"mpcexp_status", i));
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g_free(mpcname);
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/* Return the register interface MR for our caller to map behind the PPC */
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0);
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}
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static MemoryRegion *make_rtc(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size)
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{
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PL031State *rtc = opaque;
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object_initialize_child(OBJECT(mms), name, rtc, TYPE_PL031);
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sysbus_realize(SYS_BUS_DEVICE(rtc), &error_fatal);
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sysbus_connect_irq(SYS_BUS_DEVICE(rtc), 0, get_sse_irq_in(mms, 39));
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(rtc), 0);
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}
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static MemoryRegion *make_uart(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size)
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{
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PL011State *uart = opaque;
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int i = uart - &mms->uart[0];
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int irqbase = 7 + i * 6;
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SysBusDevice *s;
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object_initialize_child(OBJECT(mms), name, uart, TYPE_PL011);
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qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
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sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal);
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s = SYS_BUS_DEVICE(uart);
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sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqbase + 5)); /* combined */
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sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqbase + 0)); /* RX */
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sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqbase + 1)); /* TX */
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sysbus_connect_irq(s, 3, get_sse_irq_in(mms, irqbase + 2)); /* RT */
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sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqbase + 3)); /* MS */
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sysbus_connect_irq(s, 5, get_sse_irq_in(mms, irqbase + 4)); /* E */
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return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0);
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}
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static MemoryRegion *make_musca_a_devs(MuscaMachineState *mms, void *opaque,
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const char *name, hwaddr size)
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{
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/*
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* Create the container MemoryRegion for all the devices that live
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* behind the Musca-A PPC's single port. These devices don't have a PPC
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* port each, but we use the PPCPortInfo struct as a convenient way
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* to describe them. Note that addresses here are relative to the base
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* address of the PPC port region: 0x40100000, and devices appear both
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* at the 0x4... NS region and the 0x5... S region.
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*/
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int i;
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MemoryRegion *container = &mms->container;
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const PPCPortInfo devices[] = {
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{ "uart0", make_uart, &mms->uart[0], 0x1000, 0x1000 },
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{ "uart1", make_uart, &mms->uart[1], 0x2000, 0x1000 },
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{ "spi", make_unimp_dev, &mms->spi, 0x3000, 0x1000 },
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{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x4000, 0x1000 },
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{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x5000, 0x1000 },
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{ "i2s", make_unimp_dev, &mms->i2s, 0x6000, 0x1000 },
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{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 },
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{ "rtc", make_rtc, &mms->rtc, 0x8000, 0x1000 },
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{ "qspi", make_unimp_dev, &mms->qspi, 0xa000, 0x1000 },
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{ "timer", make_unimp_dev, &mms->timer, 0xb000, 0x1000 },
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{ "scc", make_unimp_dev, &mms->scc, 0xc000, 0x1000 },
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{ "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 },
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{ "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 },
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{ "gpio", make_unimp_dev, &mms->gpio, 0x10000, 0x1000 },
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{ "mpc0", make_mpc, &mms->mpc[0], 0x12000, 0x1000 },
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{ "mpc1", make_mpc, &mms->mpc[1], 0x13000, 0x1000 },
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};
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memory_region_init(container, OBJECT(mms), "musca-device-container", size);
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for (i = 0; i < ARRAY_SIZE(devices); i++) {
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const PPCPortInfo *pinfo = &devices[i];
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MemoryRegion *mr;
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mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
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memory_region_add_subregion(container, pinfo->addr, mr);
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}
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return &mms->container;
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}
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static void musca_init(MachineState *machine)
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{
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MuscaMachineState *mms = MUSCA_MACHINE(machine);
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MuscaMachineClass *mmc = MUSCA_MACHINE_GET_CLASS(mms);
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MemoryRegion *system_memory = get_system_memory();
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DeviceState *ssedev;
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DeviceState *dev_splitter;
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const PPCInfo *ppcs;
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int num_ppcs;
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int i;
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assert(mmc->num_irqs <= MUSCA_NUMIRQ_MAX);
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assert(mmc->num_mpcs <= MUSCA_MPC_MAX);
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mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
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clock_set_hz(mms->sysclk, SYSCLK_FRQ);
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mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
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clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
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object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
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TYPE_SSE200);
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ssedev = DEVICE(&mms->sse);
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object_property_set_link(OBJECT(&mms->sse), "memory",
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OBJECT(system_memory), &error_fatal);
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qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
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qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
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qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
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qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
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qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
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/*
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* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
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* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
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*/
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if (mmc->type == MUSCA_B1) {
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qdev_prop_set_bit(ssedev, "CPU0_FPU", true);
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qdev_prop_set_bit(ssedev, "CPU0_DSP", true);
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}
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sysbus_realize(SYS_BUS_DEVICE(&mms->sse), &error_fatal);
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/*
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* We need to create splitters to feed the IRQ inputs
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* for each CPU in the SSE-200 from each device in the board.
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*/
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for (i = 0; i < mmc->num_irqs; i++) {
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char *name = g_strdup_printf("musca-irq-splitter%d", i);
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SplitIRQ *splitter = &mms->cpu_irq_splitter[i];
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object_initialize_child_with_props(OBJECT(machine), name, splitter,
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sizeof(*splitter), TYPE_SPLIT_IRQ,
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&error_fatal, NULL);
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g_free(name);
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object_property_set_int(OBJECT(splitter), "num-lines", 2,
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&error_fatal);
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qdev_realize(DEVICE(splitter), NULL, &error_fatal);
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qdev_connect_gpio_out(DEVICE(splitter), 0,
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qdev_get_gpio_in_named(ssedev, "EXP_IRQ", i));
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qdev_connect_gpio_out(DEVICE(splitter), 1,
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qdev_get_gpio_in_named(ssedev,
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"EXP_CPU1_IRQ", i));
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}
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/*
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* The sec_resp_cfg output from the SSE-200 must be split into multiple
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* lines, one for each of the PPCs we create here.
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*/
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object_initialize_child_with_props(OBJECT(machine), "sec-resp-splitter",
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&mms->sec_resp_splitter,
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sizeof(mms->sec_resp_splitter),
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TYPE_SPLIT_IRQ, &error_fatal, NULL);
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object_property_set_int(OBJECT(&mms->sec_resp_splitter), "num-lines",
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ARRAY_SIZE(mms->ppc), &error_fatal);
|
|
qdev_realize(DEVICE(&mms->sec_resp_splitter), NULL, &error_fatal);
|
|
dev_splitter = DEVICE(&mms->sec_resp_splitter);
|
|
qdev_connect_gpio_out_named(ssedev, "sec_resp_cfg", 0,
|
|
qdev_get_gpio_in(dev_splitter, 0));
|
|
|
|
/*
|
|
* Most of the devices in the board are behind Peripheral Protection
|
|
* Controllers. The required order for initializing things is:
|
|
* + initialize the PPC
|
|
* + initialize, configure and realize downstream devices
|
|
* + connect downstream device MemoryRegions to the PPC
|
|
* + realize the PPC
|
|
* + map the PPC's MemoryRegions to the places in the address map
|
|
* where the downstream devices should appear
|
|
* + wire up the PPC's control lines to the SSE object
|
|
*
|
|
* The PPC mapping differs for the -A and -B1 variants; the -A version
|
|
* is much simpler, using only a single port of a single PPC and putting
|
|
* all the devices behind that.
|
|
*/
|
|
const PPCInfo a_ppcs[] = { {
|
|
.name = "ahb_ppcexp0",
|
|
.ports = {
|
|
{ "musca-devices", make_musca_a_devs, 0, 0x40100000, 0x100000 },
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Devices listed with an 0x4.. address appear in both the NS 0x4.. region
|
|
* and the 0x5.. S region. Devices listed with an 0x5.. address appear
|
|
* only in the S region.
|
|
*/
|
|
const PPCInfo b1_ppcs[] = { {
|
|
.name = "apb_ppcexp0",
|
|
.ports = {
|
|
{ "eflash0", make_unimp_dev, &mms->eflash[0],
|
|
0x52400000, 0x1000 },
|
|
{ "eflash1", make_unimp_dev, &mms->eflash[1],
|
|
0x52500000, 0x1000 },
|
|
{ "qspi", make_unimp_dev, &mms->qspi, 0x42800000, 0x100000 },
|
|
{ "mpc0", make_mpc, &mms->mpc[0], 0x52000000, 0x1000 },
|
|
{ "mpc1", make_mpc, &mms->mpc[1], 0x52100000, 0x1000 },
|
|
{ "mpc2", make_mpc, &mms->mpc[2], 0x52200000, 0x1000 },
|
|
{ "mpc3", make_mpc, &mms->mpc[3], 0x52300000, 0x1000 },
|
|
{ "mhu0", make_unimp_dev, &mms->mhu[0], 0x42600000, 0x100000 },
|
|
{ "mhu1", make_unimp_dev, &mms->mhu[1], 0x42700000, 0x100000 },
|
|
{ }, /* port 9: unused */
|
|
{ }, /* port 10: unused */
|
|
{ }, /* port 11: unused */
|
|
{ }, /* port 12: unused */
|
|
{ }, /* port 13: unused */
|
|
{ "mpc4", make_mpc, &mms->mpc[4], 0x52e00000, 0x1000 },
|
|
},
|
|
}, {
|
|
.name = "apb_ppcexp1",
|
|
.ports = {
|
|
{ "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 },
|
|
{ "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 },
|
|
{ "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 },
|
|
{ "i2s", make_unimp_dev, &mms->i2s, 0x40104000, 0x1000 },
|
|
{ "uart0", make_uart, &mms->uart[0], 0x40105000, 0x1000 },
|
|
{ "uart1", make_uart, &mms->uart[1], 0x40106000, 0x1000 },
|
|
{ "i2c0", make_unimp_dev, &mms->i2c[0], 0x40108000, 0x1000 },
|
|
{ "i2c1", make_unimp_dev, &mms->i2c[1], 0x40109000, 0x1000 },
|
|
{ "spi", make_unimp_dev, &mms->spi, 0x4010a000, 0x1000 },
|
|
{ "scc", make_unimp_dev, &mms->scc, 0x5010b000, 0x1000 },
|
|
{ "timer", make_unimp_dev, &mms->timer, 0x4010c000, 0x1000 },
|
|
{ "rtc", make_rtc, &mms->rtc, 0x4010d000, 0x1000 },
|
|
{ "pvt", make_unimp_dev, &mms->pvt, 0x4010e000, 0x1000 },
|
|
{ "sdio", make_unimp_dev, &mms->sdio, 0x4010f000, 0x1000 },
|
|
},
|
|
}, {
|
|
.name = "ahb_ppcexp0",
|
|
.ports = {
|
|
{ }, /* port 0: unused */
|
|
{ "gpio", make_unimp_dev, &mms->gpio, 0x41000000, 0x1000 },
|
|
},
|
|
},
|
|
};
|
|
|
|
switch (mmc->type) {
|
|
case MUSCA_A:
|
|
ppcs = a_ppcs;
|
|
num_ppcs = ARRAY_SIZE(a_ppcs);
|
|
break;
|
|
case MUSCA_B1:
|
|
ppcs = b1_ppcs;
|
|
num_ppcs = ARRAY_SIZE(b1_ppcs);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
assert(num_ppcs <= MUSCA_PPC_MAX);
|
|
|
|
for (i = 0; i < num_ppcs; i++) {
|
|
const PPCInfo *ppcinfo = &ppcs[i];
|
|
TZPPC *ppc = &mms->ppc[i];
|
|
DeviceState *ppcdev;
|
|
int port;
|
|
char *gpioname;
|
|
|
|
object_initialize_child(OBJECT(machine), ppcinfo->name, ppc,
|
|
TYPE_TZ_PPC);
|
|
ppcdev = DEVICE(ppc);
|
|
|
|
for (port = 0; port < TZ_NUM_PORTS; port++) {
|
|
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
|
|
MemoryRegion *mr;
|
|
char *portname;
|
|
|
|
if (!pinfo->devfn) {
|
|
continue;
|
|
}
|
|
|
|
mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size);
|
|
portname = g_strdup_printf("port[%d]", port);
|
|
object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
|
|
&error_fatal);
|
|
g_free(portname);
|
|
}
|
|
|
|
sysbus_realize(SYS_BUS_DEVICE(ppc), &error_fatal);
|
|
|
|
for (port = 0; port < TZ_NUM_PORTS; port++) {
|
|
const PPCPortInfo *pinfo = &ppcinfo->ports[port];
|
|
|
|
if (!pinfo->devfn) {
|
|
continue;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(ppc), port, pinfo->addr);
|
|
|
|
gpioname = g_strdup_printf("%s_nonsec", ppcinfo->name);
|
|
qdev_connect_gpio_out_named(ssedev, gpioname, port,
|
|
qdev_get_gpio_in_named(ppcdev,
|
|
"cfg_nonsec",
|
|
port));
|
|
g_free(gpioname);
|
|
gpioname = g_strdup_printf("%s_ap", ppcinfo->name);
|
|
qdev_connect_gpio_out_named(ssedev, gpioname, port,
|
|
qdev_get_gpio_in_named(ppcdev,
|
|
"cfg_ap", port));
|
|
g_free(gpioname);
|
|
}
|
|
|
|
gpioname = g_strdup_printf("%s_irq_enable", ppcinfo->name);
|
|
qdev_connect_gpio_out_named(ssedev, gpioname, 0,
|
|
qdev_get_gpio_in_named(ppcdev,
|
|
"irq_enable", 0));
|
|
g_free(gpioname);
|
|
gpioname = g_strdup_printf("%s_irq_clear", ppcinfo->name);
|
|
qdev_connect_gpio_out_named(ssedev, gpioname, 0,
|
|
qdev_get_gpio_in_named(ppcdev,
|
|
"irq_clear", 0));
|
|
g_free(gpioname);
|
|
gpioname = g_strdup_printf("%s_irq_status", ppcinfo->name);
|
|
qdev_connect_gpio_out_named(ppcdev, "irq", 0,
|
|
qdev_get_gpio_in_named(ssedev,
|
|
gpioname, 0));
|
|
g_free(gpioname);
|
|
|
|
qdev_connect_gpio_out(dev_splitter, i,
|
|
qdev_get_gpio_in_named(ppcdev,
|
|
"cfg_sec_resp", 0));
|
|
}
|
|
|
|
armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
|
|
0, 0x2000000);
|
|
}
|
|
|
|
static void musca_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
static const char * const valid_cpu_types[] = {
|
|
ARM_CPU_TYPE_NAME("cortex-m33"),
|
|
NULL
|
|
};
|
|
|
|
mc->default_cpus = 2;
|
|
mc->min_cpus = mc->default_cpus;
|
|
mc->max_cpus = mc->default_cpus;
|
|
mc->valid_cpu_types = valid_cpu_types;
|
|
mc->init = musca_init;
|
|
}
|
|
|
|
static void musca_a_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "ARM Musca-A board (dual Cortex-M33)";
|
|
mmc->type = MUSCA_A;
|
|
mmc->init_svtor = 0x10200000;
|
|
mmc->sram_addr_width = 15;
|
|
mmc->num_irqs = 64;
|
|
mmc->mpc_info = a_mpc_info;
|
|
mmc->num_mpcs = ARRAY_SIZE(a_mpc_info);
|
|
}
|
|
|
|
static void musca_b1_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
MuscaMachineClass *mmc = MUSCA_MACHINE_CLASS(oc);
|
|
|
|
mc->desc = "ARM Musca-B1 board (dual Cortex-M33)";
|
|
mmc->type = MUSCA_B1;
|
|
/*
|
|
* This matches the DAPlink firmware which boots from QSPI. There
|
|
* is also a firmware blob which boots from the eFlash, which
|
|
* uses init_svtor = 0x1A000000. QEMU doesn't currently support that,
|
|
* though we could in theory expose a machine property on the command
|
|
* line to allow the user to request eFlash boot.
|
|
*/
|
|
mmc->init_svtor = 0x10000000;
|
|
mmc->sram_addr_width = 17;
|
|
mmc->num_irqs = 96;
|
|
mmc->mpc_info = b1_mpc_info;
|
|
mmc->num_mpcs = ARRAY_SIZE(b1_mpc_info);
|
|
}
|
|
|
|
static const TypeInfo musca_info = {
|
|
.name = TYPE_MUSCA_MACHINE,
|
|
.parent = TYPE_MACHINE,
|
|
.abstract = true,
|
|
.instance_size = sizeof(MuscaMachineState),
|
|
.class_size = sizeof(MuscaMachineClass),
|
|
.class_init = musca_class_init,
|
|
};
|
|
|
|
static const TypeInfo musca_a_info = {
|
|
.name = TYPE_MUSCA_A_MACHINE,
|
|
.parent = TYPE_MUSCA_MACHINE,
|
|
.class_init = musca_a_class_init,
|
|
};
|
|
|
|
static const TypeInfo musca_b1_info = {
|
|
.name = TYPE_MUSCA_B1_MACHINE,
|
|
.parent = TYPE_MUSCA_MACHINE,
|
|
.class_init = musca_b1_class_init,
|
|
};
|
|
|
|
static void musca_machine_init(void)
|
|
{
|
|
type_register_static(&musca_info);
|
|
type_register_static(&musca_a_info);
|
|
type_register_static(&musca_b1_info);
|
|
}
|
|
|
|
type_init(musca_machine_init);
|