26a76461f2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
401 lines
11 KiB
C
401 lines
11 KiB
C
/*
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* QEMU Sparc SLAVIO interrupt controller emulation
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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//#define DEBUG_IRQ_COUNT
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, args...) \
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do { printf("IRQ: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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/*
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* Registers of interrupt controller in sun4m.
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*
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* This is the interrupt controller part of chip STP2001 (Slave I/O), also
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* produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* There is a system master controller and one for each cpu.
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*
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*/
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#define MAX_CPUS 16
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typedef struct SLAVIO_INTCTLState {
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uint32_t intreg_pending[MAX_CPUS];
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uint32_t intregm_pending;
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uint32_t intregm_disabled;
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uint32_t target_cpu;
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#ifdef DEBUG_IRQ_COUNT
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uint64_t irq_count[32];
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#endif
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CPUState *cpu_envs[MAX_CPUS];
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} SLAVIO_INTCTLState;
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#define INTCTL_MAXADDR 0xf
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#define INTCTLM_MAXADDR 0xf
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static void slavio_check_interrupts(void *opaque);
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// per-cpu interrupt controller
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static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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int cpu;
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cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
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saddr = (addr & INTCTL_MAXADDR) >> 2;
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switch (saddr) {
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case 0:
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return s->intreg_pending[cpu];
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default:
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break;
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}
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return 0;
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}
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static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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int cpu;
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cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
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saddr = (addr & INTCTL_MAXADDR) >> 2;
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switch (saddr) {
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case 1: // clear pending softints
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if (val & 0x4000)
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val |= 80000000;
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val &= 0xfffe0000;
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s->intreg_pending[cpu] &= ~val;
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DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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break;
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case 2: // set softint
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val &= 0xfffe0000;
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s->intreg_pending[cpu] |= val;
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slavio_check_interrupts(s);
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DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
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slavio_intctl_mem_readl,
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slavio_intctl_mem_readl,
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slavio_intctl_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
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slavio_intctl_mem_writel,
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slavio_intctl_mem_writel,
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slavio_intctl_mem_writel,
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};
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// master system interrupt controller
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static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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saddr = (addr & INTCTLM_MAXADDR) >> 2;
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switch (saddr) {
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case 0:
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return s->intregm_pending & 0x7fffffff;
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case 1:
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return s->intregm_disabled;
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case 4:
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return s->target_cpu;
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default:
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break;
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}
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return 0;
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}
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static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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SLAVIO_INTCTLState *s = opaque;
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uint32_t saddr;
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saddr = (addr & INTCTLM_MAXADDR) >> 2;
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switch (saddr) {
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case 2: // clear (enable)
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// Force clear unused bits
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val &= ~0x4fb2007f;
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s->intregm_disabled &= ~val;
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DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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slavio_check_interrupts(s);
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break;
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case 3: // set (disable, clear pending)
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// Force clear unused bits
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val &= ~0x4fb2007f;
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s->intregm_disabled |= val;
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s->intregm_pending &= ~val;
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DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
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break;
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case 4:
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s->target_cpu = val & (MAX_CPUS - 1);
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DPRINTF("Set master irq cpu %d\n", s->target_cpu);
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
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slavio_intctlm_mem_readl,
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slavio_intctlm_mem_readl,
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slavio_intctlm_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
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slavio_intctlm_mem_writel,
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slavio_intctlm_mem_writel,
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slavio_intctlm_mem_writel,
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};
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void slavio_pic_info(void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
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}
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term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
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}
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void slavio_irq_info(void *opaque)
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{
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#ifndef DEBUG_IRQ_COUNT
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term_printf("irq statistic code not compiled.\n");
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#else
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SLAVIO_INTCTLState *s = opaque;
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int i;
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int64_t count;
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term_printf("IRQ statistics:\n");
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for (i = 0; i < 32; i++) {
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count = s->irq_count[i];
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if (count > 0)
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term_printf("%2d: %" PRId64 "\n", i, count);
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}
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#endif
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}
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static const uint32_t intbit_to_level[32] = {
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2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
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6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
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};
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static void slavio_check_interrupts(void *opaque)
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{
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CPUState *env;
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SLAVIO_INTCTLState *s = opaque;
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uint32_t pending = s->intregm_pending;
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unsigned int i, j, max = 0;
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pending &= ~s->intregm_disabled;
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if (pending && !(s->intregm_disabled & 0x80000000)) {
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for (i = 0; i < 32; i++) {
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if (pending & (1 << i)) {
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if (max < intbit_to_level[i])
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max = intbit_to_level[i];
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}
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}
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env = s->cpu_envs[s->target_cpu];
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if (!env) {
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DPRINTF("No CPU %d, not triggered (pending %x)\n", s->target_cpu, pending);
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}
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else {
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if (env->halted)
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env->halted = 0;
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered CPU %d pil %d\n", s->target_cpu, max);
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[max]++;
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#endif
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env->interrupt_index = TT_EXTINT | max;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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else
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DPRINTF("Not triggered (pending %x), pending exception %x\n", pending, env->interrupt_index);
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}
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}
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else
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DPRINTF("Not triggered (pending %x), disabled %x\n", pending, s->intregm_disabled);
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for (i = 0; i < MAX_CPUS; i++) {
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max = 0;
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env = s->cpu_envs[i];
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if (!env)
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continue;
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for (j = 17; j < 32; j++) {
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if (s->intreg_pending[i] & (1 << j)) {
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if (max < j - 16)
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max = j - 16;
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}
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}
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if (max > 0) {
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if (env->halted)
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env->halted = 0;
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if (env->interrupt_index == 0) {
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DPRINTF("Triggered softint %d for cpu %d (pending %x)\n", max, i, pending);
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#ifdef DEBUG_IRQ_COUNT
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s->irq_count[max]++;
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#endif
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env->interrupt_index = TT_EXTINT | max;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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}
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}
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/*
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* "irq" here is the bit number in the system interrupt register to
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* separate serial and keyboard interrupts sharing a level.
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*/
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void slavio_pic_set_irq(void *opaque, int irq, int level)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set cpu %d irq %d level %d\n", s->target_cpu, irq, level);
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if (irq < 32) {
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uint32_t mask = 1 << irq;
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uint32_t pil = intbit_to_level[irq];
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if (pil > 0) {
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if (level) {
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s->intregm_pending |= mask;
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s->intreg_pending[s->target_cpu] |= 1 << pil;
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}
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else {
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s->intregm_pending &= ~mask;
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s->intreg_pending[s->target_cpu] &= ~(1 << pil);
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}
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}
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}
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slavio_check_interrupts(s);
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}
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void slavio_pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu)
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{
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SLAVIO_INTCTLState *s = opaque;
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DPRINTF("Set cpu %d local irq %d level %d\n", cpu, irq, level);
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if (cpu == (unsigned int)-1) {
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slavio_pic_set_irq(opaque, irq, level);
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return;
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}
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if (irq < 32) {
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uint32_t pil = intbit_to_level[irq];
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if (pil > 0) {
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if (level) {
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s->intreg_pending[cpu] |= 1 << pil;
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}
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else {
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s->intreg_pending[cpu] &= ~(1 << pil);
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}
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}
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}
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slavio_check_interrupts(s);
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}
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static void slavio_intctl_save(QEMUFile *f, void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_put_be32s(f, &s->intreg_pending[i]);
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}
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qemu_put_be32s(f, &s->intregm_pending);
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qemu_put_be32s(f, &s->intregm_disabled);
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qemu_put_be32s(f, &s->target_cpu);
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}
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static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for (i = 0; i < MAX_CPUS; i++) {
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qemu_get_be32s(f, &s->intreg_pending[i]);
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}
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qemu_get_be32s(f, &s->intregm_pending);
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qemu_get_be32s(f, &s->intregm_disabled);
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qemu_get_be32s(f, &s->target_cpu);
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return 0;
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}
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static void slavio_intctl_reset(void *opaque)
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{
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SLAVIO_INTCTLState *s = opaque;
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int i;
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for (i = 0; i < MAX_CPUS; i++) {
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s->intreg_pending[i] = 0;
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}
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s->intregm_disabled = ~0xffb2007f;
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s->intregm_pending = 0;
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s->target_cpu = 0;
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}
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void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env)
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{
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SLAVIO_INTCTLState *s = opaque;
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s->cpu_envs[cpu] = env;
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}
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void *slavio_intctl_init(uint32_t addr, uint32_t addrg)
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{
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int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
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SLAVIO_INTCTLState *s;
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s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
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if (!s)
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return NULL;
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for (i = 0; i < MAX_CPUS; i++) {
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slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
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cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_MAXADDR, slavio_intctl_io_memory);
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}
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slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
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cpu_register_physical_memory(addrg, INTCTLM_MAXADDR, slavio_intctlm_io_memory);
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register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
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qemu_register_reset(slavio_intctl_reset, s);
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slavio_intctl_reset(s);
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return s;
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}
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