3e62a32ddb
The testcases for ASPEED SMC model were placed in aspeed_smc-test.c. However, this test file only supports for ARM32. To support all ASPEED SOCs such as AST2700 whose CPU architecture is aarch64, introduces a new aspeed-smc-utils source file and move all common APIs and testcases from aspeed_smc-test.c to aspeed-smc-utils.c. Finally, users are able to re-used these testcase for AST2700 and future ASPEED SOCs testing. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241127091543.1243114-10-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
96 lines
3.1 KiB
C
96 lines
3.1 KiB
C
/*
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* QTest testcase for the M25P80 Flash (Using the Aspeed SPI
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* Controller)
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef TESTS_ASPEED_SMC_UTILS_H
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#define TESTS_ASPEED_SMC_UTILS_H
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#include "qemu/osdep.h"
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#include "qemu/bswap.h"
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#include "libqtest-single.h"
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#include "qemu/bitops.h"
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/*
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* ASPEED SPI Controller registers
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*/
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#define R_CONF 0x00
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#define CONF_ENABLE_W0 16
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#define R_CE_CTRL 0x04
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#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */
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#define R_CTRL0 0x10
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#define CTRL_IO_QUAD_IO BIT(31)
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#define CTRL_CE_STOP_ACTIVE BIT(2)
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#define CTRL_READMODE 0x0
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#define CTRL_FREADMODE 0x1
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#define CTRL_WRITEMODE 0x2
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#define CTRL_USERMODE 0x3
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#define SR_WEL BIT(1)
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/*
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* Flash commands
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*/
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enum {
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JEDEC_READ = 0x9f,
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RDSR = 0x5,
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WRDI = 0x4,
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BULK_ERASE = 0xc7,
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READ = 0x03,
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PP = 0x02,
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WRSR = 0x1,
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WREN = 0x6,
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SRWD = 0x80,
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RESET_ENABLE = 0x66,
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RESET_MEMORY = 0x99,
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EN_4BYTE_ADDR = 0xB7,
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ERASE_SECTOR = 0xd8,
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};
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#define CTRL_IO_MODE_MASK (BIT(31) | BIT(30) | BIT(29) | BIT(28))
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#define FLASH_PAGE_SIZE 256
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typedef struct AspeedSMCTestData {
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QTestState *s;
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uint64_t spi_base;
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uint64_t flash_base;
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uint32_t jedec_id;
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char *tmp_path;
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uint8_t cs;
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const char *node;
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uint32_t page_addr;
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} AspeedSMCTestData;
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void aspeed_smc_test_read_jedec(const void *data);
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void aspeed_smc_test_erase_sector(const void *data);
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void aspeed_smc_test_erase_all(const void *data);
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void aspeed_smc_test_write_page(const void *data);
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void aspeed_smc_test_read_page_mem(const void *data);
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void aspeed_smc_test_write_page_mem(const void *data);
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void aspeed_smc_test_read_status_reg(const void *data);
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void aspeed_smc_test_status_reg_write_protection(const void *data);
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void aspeed_smc_test_write_block_protect(const void *data);
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void aspeed_smc_test_write_block_protect_bottom_bit(const void *data);
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void aspeed_smc_test_write_page_qpi(const void *data);
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#endif /* TESTS_ASPEED_SMC_UTILS_H */
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