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FRET-qemu/target/riscv
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Richard Henderson e4a8e093dc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 
Convert all targets simultaneously, as the gen_intermediate_code
function disappears from the target.  While there are possible
workarounds, they're larger than simply performing the conversion.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-24 08:32:15 -08:00
..
insn_trans
target/riscv: Set vdata.vm field for vector load/store whole register instructions
2024-11-07 08:21:14 +10:00
kvm
Accel & Exec patch queue
2024-12-21 11:07:00 -05:00
tcg
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
2024-12-24 08:32:15 -08:00
arch_dump.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
2024-12-20 11:22:47 +10:00
cpu_cfg.h
target/riscv: add ssstateen
2024-12-20 11:22:47 +10:00
cpu_helper.c
Accel & Exec patch queue
2024-12-21 11:07:00 -05:00
cpu_user.h
target/riscv: zicfilp lpad impl and branch tracking
2024-10-30 11:22:08 +10:00
cpu_vendorid.h
target/riscv: add Ventana's Veyron V1 CPU
2023-05-05 10:49:50 +10:00
cpu-param.h
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
2024-09-20 10:11:59 +03:00
cpu-qom.h
target/riscv: add support for RV64 Xiangshan Nanhu CPU
2024-12-20 11:22:47 +10:00
cpu.c
Accel & Exec patch queue
2024-12-21 11:07:00 -05:00
cpu.h
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
2024-12-24 08:32:15 -08:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
Accel & Exec patch queue
2024-12-21 11:07:00 -05:00
debug.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
debug.h
target/riscv: Add textra matching condition for the triggers
2024-10-02 15:11:51 +10:00
fpu_helper.c
target/riscv: Fix froundnx.h nanbox check
2024-06-26 23:02:35 +10:00
gdbstub.c
riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
2024-06-03 11:12:12 +10:00
helper.h
target/riscv: Raise exceptions on wrs.nto
2024-06-03 11:12:11 +10:00
insn16.decode
target/riscv: compressed encodings for sspush and sspopchk
2024-10-30 11:22:08 +10:00
insn32.decode
target/riscv: implement zicfiss instructions
2024-10-30 11:22:08 +10:00
instmap.h
…
internals.h
target/riscv: Include missing headers in 'internals.h'
2024-12-20 11:22:47 +10:00
Kconfig
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-10-02 15:11:51 +10:00
m128_helper.c
target/helpers: Remove unnecessary 'qemu/main-loop.h' header
2023-08-31 19:47:43 +02:00
machine.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
meson.build
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
monitor.c
target/riscv: remove break after g_assert_not_reached()
2024-09-24 13:53:35 +02:00
op_helper.c
target/riscv: save and restore elp state on priv transitions
2024-10-30 11:22:08 +10:00
pmp.c
target/riscv: Introduce elp state and enabling controls for zicfilp
2024-10-30 11:22:08 +10:00
pmp.h
target/riscv: Introduce elp state and enabling controls for zicfilp
2024-10-30 11:22:08 +10:00
pmu.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
pmu.h
target/riscv: More accurately model priv mode filtering.
2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c
include: Rename sysemu/ -> system/
2024-12-20 17:44:56 +01:00
sbi_ecall_interface.h
target/riscv/kvm: implement SBI debug console (DBCN) calls
2024-06-03 11:12:11 +10:00
th_csr.c
riscv: thead: Add th.sxstatus CSR emulation
2024-06-03 11:12:12 +10:00
time_helper.c
target/riscv: Stop timer with infinite timecmp
2024-10-02 15:11:51 +10:00
time_helper.h
…
trace-events
…
trace.h
…
translate.c
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
2024-12-24 08:32:15 -08:00
vcrypto_helper.c
target/riscv/vector_helpers: do early exit when vstart >= vl
2024-03-22 15:20:02 +10:00
vector_helper.c
target/riscv: Inline unit-stride ld/st and corresponding functions for performance
2024-11-07 12:33:44 +10:00
vector_internals.c
target/riscv: Fix the element agnostic function problem
2024-06-03 11:12:12 +10:00
vector_internals.h
target/riscv: Include missing headers in 'vector_internals.h'
2024-12-20 11:22:47 +10:00
xthead.decode
…
XVentanaCondOps.decode
…
zce_helper.c
…