53c1557b23
The current approach of using qemu_chr_fe_write() and ignoring the return values results in dropped characters [1]. Let's update the SiFive UART to use a async sifive_uart_xmit() function to transmit the characters and apply back pressure to the guest with the SIFIVE_UART_TXFIFO_FULL status. This should avoid dropped characters and more realisticly model the hardware. 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910045419.1252277-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* SiFive UART interface
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*
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* Copyright (c) 2016 Stefan O'Rear
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_UART_H
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#define HW_SIFIVE_UART_H
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#include "chardev/char-fe.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#include "qemu/fifo8.h"
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enum {
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SIFIVE_UART_TXFIFO = 0,
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SIFIVE_UART_RXFIFO = 4,
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SIFIVE_UART_TXCTRL = 8,
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SIFIVE_UART_TXMARK = 10,
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SIFIVE_UART_RXCTRL = 12,
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SIFIVE_UART_RXMARK = 14,
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SIFIVE_UART_IE = 16,
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SIFIVE_UART_IP = 20,
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SIFIVE_UART_DIV = 24,
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SIFIVE_UART_MAX = 32
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};
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enum {
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SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */
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SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */
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};
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enum {
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SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */
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SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
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};
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#define SIFIVE_UART_TXFIFO_FULL 0x80000000
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#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
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#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
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#define SIFIVE_UART_RX_FIFO_SIZE 8
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#define SIFIVE_UART_TX_FIFO_SIZE 8
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#define TYPE_SIFIVE_UART "riscv.sifive.uart"
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OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
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struct SiFiveUARTState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq irq;
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MemoryRegion mmio;
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CharBackend chr;
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uint32_t txfifo;
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uint32_t ie;
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uint32_t ip;
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uint32_t txctrl;
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uint32_t rxctrl;
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uint32_t div;
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uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
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uint8_t rx_fifo_len;
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Fifo8 tx_fifo;
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QEMUTimer *fifo_trigger_handle;
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};
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SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
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Chardev *chr, qemu_irq irq);
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#endif
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