d6ccfc7e67
Connect the CRL (Clock Reset LPD) to the Versal SoC. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
/*
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* Model of the Xilinx Versal
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*
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* Copyright (c) 2018 Xilinx Inc.
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* Written by Edgar E. Iglesias
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#ifndef XLNX_VERSAL_H
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#define XLNX_VERSAL_H
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#include "hw/sysbus.h"
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#include "hw/arm/boot.h"
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#include "hw/cpu/cluster.h"
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#include "hw/or-irq.h"
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#include "hw/sd/sdhci.h"
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#include "hw/intc/arm_gicv3.h"
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#include "hw/char/pl011.h"
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#include "hw/dma/xlnx-zdma.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/rtc/xlnx-zynqmp-rtc.h"
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#include "qom/object.h"
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#include "hw/usb/xlnx-usb-subsystem.h"
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#include "hw/misc/xlnx-versal-xramc.h"
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#include "hw/nvram/xlnx-bbram.h"
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#include "hw/nvram/xlnx-versal-efuse.h"
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#include "hw/ssi/xlnx-versal-ospi.h"
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#include "hw/dma/xlnx_csu_dma.h"
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#include "hw/misc/xlnx-versal-crl.h"
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#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
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#define TYPE_XLNX_VERSAL "xlnx-versal"
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OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
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#define XLNX_VERSAL_NR_ACPUS 2
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#define XLNX_VERSAL_NR_RCPUS 2
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#define XLNX_VERSAL_NR_UARTS 2
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#define XLNX_VERSAL_NR_GEMS 2
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#define XLNX_VERSAL_NR_ADMAS 8
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#define XLNX_VERSAL_NR_SDS 2
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#define XLNX_VERSAL_NR_XRAM 4
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#define XLNX_VERSAL_NR_IRQS 192
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struct Versal {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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struct {
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struct {
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MemoryRegion mr;
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CPUClusterState cluster;
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ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
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GICv3State gic;
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} apu;
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} fpd;
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MemoryRegion mr_ps;
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struct {
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/* 4 ranges to access DDR. */
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MemoryRegion mr_ddr_ranges[4];
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} noc;
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struct {
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MemoryRegion mr_ocm;
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struct {
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PL011State uart[XLNX_VERSAL_NR_UARTS];
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CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
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XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
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VersalUsb2 usb;
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} iou;
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/* Real-time Processing Unit. */
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struct {
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MemoryRegion mr;
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MemoryRegion mr_ps_alias;
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CPUClusterState cluster;
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ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
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} rpu;
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struct {
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qemu_or_irq irq_orgate;
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XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
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} xram;
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XlnxVersalCRL crl;
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} lpd;
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/* The Platform Management Controller subsystem. */
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struct {
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struct {
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SDHCIState sd[XLNX_VERSAL_NR_SDS];
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XlnxVersalPmcIouSlcr slcr;
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struct {
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XlnxVersalOspi ospi;
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XlnxCSUDMA dma_src;
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XlnxCSUDMA dma_dst;
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MemoryRegion linear_mr;
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qemu_or_irq irq_orgate;
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} ospi;
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} iou;
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XlnxZynqMPRTC rtc;
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XlnxBBRam bbram;
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XlnxEFuse efuse;
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XlnxVersalEFuseCtrl efuse_ctrl;
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XlnxVersalEFuseCache efuse_cache;
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qemu_or_irq apb_irq_orgate;
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} pmc;
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struct {
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MemoryRegion *mr_ddr;
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} cfg;
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};
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/* Memory-map and IRQ definitions. Copied a subset from
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* auto-generated files. */
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#define VERSAL_GIC_MAINT_IRQ 9
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#define VERSAL_TIMER_VIRT_IRQ 11
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#define VERSAL_TIMER_S_EL1_IRQ 13
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#define VERSAL_TIMER_NS_EL1_IRQ 14
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#define VERSAL_TIMER_NS_EL2_IRQ 10
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#define VERSAL_CRL_IRQ 10
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#define VERSAL_UART0_IRQ_0 18
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#define VERSAL_UART1_IRQ_0 19
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#define VERSAL_USB0_IRQ_0 22
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#define VERSAL_GEM0_IRQ_0 56
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#define VERSAL_GEM0_WAKE_IRQ_0 57
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#define VERSAL_GEM1_IRQ_0 58
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#define VERSAL_GEM1_WAKE_IRQ_0 59
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#define VERSAL_ADMA_IRQ_0 60
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#define VERSAL_XRAM_IRQ_0 79
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#define VERSAL_PMC_APB_IRQ 121
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#define VERSAL_OSPI_IRQ 124
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#define VERSAL_SD0_IRQ_0 126
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#define VERSAL_EFUSE_IRQ 139
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#define VERSAL_RTC_ALARM_IRQ 142
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#define VERSAL_RTC_SECONDS_IRQ 143
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/* Architecturally reserved IRQs suitable for virtualization. */
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#define VERSAL_RSVD_IRQ_FIRST 111
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#define VERSAL_RSVD_IRQ_LAST 118
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#define MM_TOP_RSVD 0xa0000000U
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#define MM_TOP_RSVD_SIZE 0x4000000
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#define MM_GIC_APU_DIST_MAIN 0xf9000000U
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#define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
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#define MM_GIC_APU_REDIST_0 0xf9080000U
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#define MM_GIC_APU_REDIST_0_SIZE 0x80000
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#define MM_UART0 0xff000000U
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#define MM_UART0_SIZE 0x10000
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#define MM_UART1 0xff010000U
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#define MM_UART1_SIZE 0x10000
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#define MM_GEM0 0xff0c0000U
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#define MM_GEM0_SIZE 0x10000
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#define MM_GEM1 0xff0d0000U
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#define MM_GEM1_SIZE 0x10000
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#define MM_ADMA_CH0 0xffa80000U
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#define MM_ADMA_CH0_SIZE 0x10000
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#define MM_OCM 0xfffc0000U
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#define MM_OCM_SIZE 0x40000
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#define MM_XRAM 0xfe800000
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#define MM_XRAMC 0xff8e0000
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#define MM_XRAMC_SIZE 0x10000
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#define MM_USB2_CTRL_REGS 0xFF9D0000
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#define MM_USB2_CTRL_REGS_SIZE 0x10000
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#define MM_USB_0 0xFE200000
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#define MM_USB_0_SIZE 0x10000
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#define MM_TOP_DDR 0x0
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#define MM_TOP_DDR_SIZE 0x80000000U
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#define MM_TOP_DDR_2 0x800000000ULL
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#define MM_TOP_DDR_2_SIZE 0x800000000ULL
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#define MM_TOP_DDR_3 0xc000000000ULL
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#define MM_TOP_DDR_3_SIZE 0x4000000000ULL
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#define MM_TOP_DDR_4 0x10000000000ULL
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#define MM_TOP_DDR_4_SIZE 0xb780000000ULL
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#define MM_PSM_START 0xffc80000U
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#define MM_PSM_END 0xffcf0000U
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#define MM_CRL 0xff5e0000U
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#define MM_CRL_SIZE 0x300000
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#define MM_IOU_SCNTR 0xff130000U
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#define MM_IOU_SCNTR_SIZE 0x10000
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#define MM_IOU_SCNTRS 0xff140000U
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#define MM_IOU_SCNTRS_SIZE 0x10000
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#define MM_FPD_CRF 0xfd1a0000U
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#define MM_FPD_CRF_SIZE 0x140000
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#define MM_FPD_FPD_APU 0xfd5c0000
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#define MM_FPD_FPD_APU_SIZE 0x100
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#define MM_PMC_PMC_IOU_SLCR 0xf1060000
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#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000
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#define MM_PMC_OSPI 0xf1010000
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#define MM_PMC_OSPI_SIZE 0x10000
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#define MM_PMC_OSPI_DAC 0xc0000000
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#define MM_PMC_OSPI_DAC_SIZE 0x20000000
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#define MM_PMC_OSPI_DMA_DST 0xf1011800
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#define MM_PMC_OSPI_DMA_SRC 0xf1011000
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#define MM_PMC_SD0 0xf1040000U
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#define MM_PMC_SD0_SIZE 0x10000
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#define MM_PMC_BBRAM_CTRL 0xf11f0000
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#define MM_PMC_BBRAM_CTRL_SIZE 0x00050
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#define MM_PMC_EFUSE_CTRL 0xf1240000
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#define MM_PMC_EFUSE_CTRL_SIZE 0x00104
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#define MM_PMC_EFUSE_CACHE 0xf1250000
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#define MM_PMC_EFUSE_CACHE_SIZE 0x00C00
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#define MM_PMC_CRP 0xf1260000U
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#define MM_PMC_CRP_SIZE 0x10000
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#define MM_PMC_RTC 0xf12a0000
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#define MM_PMC_RTC_SIZE 0x10000
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#endif
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