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Robert Hoo 8c80c99fcc i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES 
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].

https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-08-16 13:43:01 -03:00
..
alpha
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
arm
target/arm: Fix aa64 FCADD and FCMLA decode
2018-08-16 14:29:58 +01:00
cris
tcg-next queue
2018-06-04 11:28:31 +01:00
hppa
tcg-next queue
2018-06-04 11:28:31 +01:00
i386
i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
2018-08-16 13:43:01 -03:00
lm32
tcg-next queue
2018-06-04 11:28:31 +01:00
m68k
target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn
2018-06-11 12:43:42 +02:00
microblaze
target-microblaze: Rework NOP/zero instruction handling
2018-06-15 09:05:00 +02:00
mips
target/mips: Fix gdbstub to read/write 64 bit FP registers
2018-06-27 20:13:50 +02:00
moxie
tcg-next queue
2018-06-04 11:28:31 +01:00
nios2
tcg-next queue
2018-06-04 11:28:31 +01:00
openrisc
target/openrisc: Fix writes to interrupt mask register
2018-07-03 22:40:33 +09:00
ppc
target/ppc: fix build on ppc64 host
2018-07-07 12:12:27 +10:00
riscv
RISC-V: Add trailing '\n' to qemu_log() calls
2018-06-08 13:15:33 +01:00
s390x
s390x/cpumodel: fix segmentation fault when baselining models
2018-07-18 14:20:02 +02:00
sh4
target/sh4: Fix translator.c assertion failure for gUSA
2018-07-09 10:34:04 -07:00
sparc
SPARC64: add icount support
2018-06-17 11:13:06 +01:00
tilegx
tcg-next queue
2018-06-04 11:28:31 +01:00
tricore
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
unicore32
tcg: Pass tb and index to tcg_gen_exit_tb separately
2018-06-01 15:15:27 -07:00
xtensa
target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn
2018-08-06 19:07:21 +01:00