The PolarFire SoC DDR Memory Controller mainly includes 2 modules, called SGMII PHY module and the CFG module, as documented in the chipset datasheet. This creates a single file that groups these 2 modules, providing the minimum functionalities that make the HSS DDR initialization codes happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
		
			
				
	
	
		
			57 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			57 lines
		
	
	
		
			1.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * Microchip PolarFire SoC DDR Memory Controller module emulation
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 *
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 * Copyright (c) 2020 Wind River Systems, Inc.
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 *
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 * Author:
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 *   Bin Meng <bin.meng@windriver.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef MCHP_PFSOC_DMC_H
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#define MCHP_PFSOC_DMC_H
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/* DDR SGMII PHY module */
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#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE   0x1000
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typedef struct MchpPfSoCDdrSgmiiPhyState {
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    SysBusDevice parent;
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    MemoryRegion sgmii_phy;
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} MchpPfSoCDdrSgmiiPhyState;
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#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
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#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
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    OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
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                 TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
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/* DDR CFG module */
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#define MCHP_PFSOC_DDR_CFG_REG_SIZE         0x40000
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typedef struct MchpPfSoCDdrCfgState {
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    SysBusDevice parent;
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    MemoryRegion cfg;
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} MchpPfSoCDdrCfgState;
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#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
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#define MCHP_PFSOC_DDR_CFG(obj) \
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    OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
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                 TYPE_MCHP_PFSOC_DDR_CFG)
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#endif /* MCHP_PFSOC_DMC_H */
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