6096cf7877
The way that Xen handles MSI PIRQs is kind of awful.
There is a special MSI message which targets a PIRQ. The vector in the
low bits of data must be zero. The low 8 bits of the PIRQ# are in the
destination ID field, the extended destination ID field is unused, and
instead the high bits of the PIRQ# are in the high 32 bits of the address.
Using the high bits of the address means that we can't intercept and
translate these messages in kvm_send_msi(), because they won't be caught
by the APIC — addresses like 0x1000fee46000 aren't in the APIC's range.
So we catch them in pci_msi_trigger() instead, and deliver the event
channel directly.
That isn't even the worst part. The worst part is that Xen snoops on
writes to devices' MSI vectors while they are *masked*. When a MSI
message is written which looks like it targets a PIRQ, it remembers
the device and vector for later.
When the guest makes a hypercall to bind that PIRQ# (snooped from a
marked MSI vector) to an event channel port, Xen *unmasks* that MSI
vector on the device. Xen guests using PIRQ delivery of MSI don't
ever actually unmask the MSI for themselves.
Now that this is working we can finally enable XENFEAT_hvm_pirqs and
let the guest use it all.
Tested with passthrough igb and emulated e1000e + AHCI.
CPU0 CPU1
0: 65 0 IO-APIC 2-edge timer
1: 0 14 xen-pirq 1-ioapic-edge i8042
4: 0 846 xen-pirq 4-ioapic-edge ttyS0
8: 1 0 xen-pirq 8-ioapic-edge rtc0
9: 0 0 xen-pirq 9-ioapic-level acpi
12: 257 0 xen-pirq 12-ioapic-edge i8042
24: 9600 0 xen-percpu -virq timer0
25: 2758 0 xen-percpu -ipi resched0
26: 0 0 xen-percpu -ipi callfunc0
27: 0 0 xen-percpu -virq debug0
28: 1526 0 xen-percpu -ipi callfuncsingle0
29: 0 0 xen-percpu -ipi spinlock0
30: 0 8608 xen-percpu -virq timer1
31: 0 874 xen-percpu -ipi resched1
32: 0 0 xen-percpu -ipi callfunc1
33: 0 0 xen-percpu -virq debug1
34: 0 1617 xen-percpu -ipi callfuncsingle1
35: 0 0 xen-percpu -ipi spinlock1
36: 8 0 xen-dyn -event xenbus
37: 0 6046 xen-pirq -msi ahci[0000:00:03.0]
38: 1 0 xen-pirq -msi-x ens4
39: 0 73 xen-pirq -msi-x ens4-rx-0
40: 14 0 xen-pirq -msi-x ens4-rx-1
41: 0 32 xen-pirq -msi-x ens4-tx-0
42: 47 0 xen-pirq -msi-x ens4-tx-1
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
|
|
* QEMU KVM support -- x86 specific functions.
|
|
*
|
|
* Copyright (c) 2012 Linaro Limited
|
|
*
|
|
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
|
* See the COPYING file in the top-level directory.
|
|
*
|
|
*/
|
|
|
|
#ifndef QEMU_KVM_I386_H
|
|
#define QEMU_KVM_I386_H
|
|
|
|
#include "sysemu/kvm.h"
|
|
|
|
#define kvm_apic_in_kernel() (kvm_irqchip_in_kernel())
|
|
|
|
#ifdef CONFIG_KVM
|
|
|
|
#define kvm_pit_in_kernel() \
|
|
(kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
|
|
#define kvm_pic_in_kernel() \
|
|
(kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
|
|
#define kvm_ioapic_in_kernel() \
|
|
(kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
|
|
|
|
#else
|
|
|
|
#define kvm_pit_in_kernel() 0
|
|
#define kvm_pic_in_kernel() 0
|
|
#define kvm_ioapic_in_kernel() 0
|
|
|
|
#endif /* CONFIG_KVM */
|
|
|
|
bool kvm_has_smm(void);
|
|
bool kvm_has_adjust_clock(void);
|
|
bool kvm_has_adjust_clock_stable(void);
|
|
bool kvm_has_exception_payload(void);
|
|
void kvm_synchronize_all_tsc(void);
|
|
void kvm_arch_reset_vcpu(X86CPU *cs);
|
|
void kvm_arch_after_reset_vcpu(X86CPU *cpu);
|
|
void kvm_arch_do_init_vcpu(X86CPU *cs);
|
|
|
|
void kvm_put_apicbase(X86CPU *cpu, uint64_t value);
|
|
|
|
bool kvm_enable_x2apic(void);
|
|
bool kvm_has_x2apic_api(void);
|
|
bool kvm_has_waitpkg(void);
|
|
|
|
bool kvm_hv_vpindex_settable(void);
|
|
bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp);
|
|
|
|
uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address);
|
|
void kvm_update_msi_routes_all(void *private, bool global,
|
|
uint32_t index, uint32_t mask);
|
|
|
|
bool kvm_enable_sgx_provisioning(KVMState *s);
|
|
void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask);
|
|
|
|
typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
|
|
typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
|
|
typedef struct kvm_msr_handlers {
|
|
uint32_t msr;
|
|
QEMURDMSRHandler *rdmsr;
|
|
QEMUWRMSRHandler *wrmsr;
|
|
} KVMMSRHandlers;
|
|
|
|
bool kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
|
|
QEMUWRMSRHandler *wrmsr);
|
|
|
|
void kvm_set_max_apic_id(uint32_t max_apic_id);
|
|
|
|
#endif
|