Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
		
			
				
	
	
		
			153 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			153 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * QEMU PowerPC MPC8544 global util pseudo-device
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 *
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 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
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 *
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 * Author: Alexander Graf, <alex@csgraf.de>
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 *
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 * This is free software; you can redistribute it and/or modify
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 * it under the terms of  the GNU General  Public License as published by
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 * the Free Software Foundation;  either version 2 of the  License, or
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 * (at your option) any later version.
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 *
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 * *****************************************************************
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 *
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 * The documentation for this device is noted in the MPC8544 documentation,
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 * file name "MPC8544ERM.pdf". You can easily find it on the web.
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 *
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "system/runstate.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define MPC8544_GUTS_MMIO_SIZE        0x1000
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#define MPC8544_GUTS_RSTCR_RESET      0x02
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#define MPC8544_GUTS_ADDR_PORPLLSR    0x00
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REG32(GUTS_PORPLLSR, 0x00)
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    FIELD(GUTS_PORPLLSR, E500_1_RATIO, 24, 6)
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    FIELD(GUTS_PORPLLSR, E500_0_RATIO, 16, 6)
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    FIELD(GUTS_PORPLLSR, DDR_RATIO, 9, 5)
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    FIELD(GUTS_PORPLLSR, PLAT_RATIO, 1, 5)
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#define MPC8544_GUTS_ADDR_PORBMSR     0x04
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#define MPC8544_GUTS_ADDR_PORIMPSCR   0x08
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#define MPC8544_GUTS_ADDR_PORDEVSR    0x0C
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#define MPC8544_GUTS_ADDR_PORDBGMSR   0x10
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#define MPC8544_GUTS_ADDR_PORDEVSR2   0x14
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#define MPC8544_GUTS_ADDR_GPPORCR     0x20
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#define MPC8544_GUTS_ADDR_GPIOCR      0x30
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#define MPC8544_GUTS_ADDR_GPOUTDR     0x40
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#define MPC8544_GUTS_ADDR_GPINDR      0x50
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#define MPC8544_GUTS_ADDR_PMUXCR      0x60
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#define MPC8544_GUTS_ADDR_DEVDISR     0x70
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#define MPC8544_GUTS_ADDR_POWMGTCSR   0x80
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#define MPC8544_GUTS_ADDR_MCPSUMR     0x90
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#define MPC8544_GUTS_ADDR_RSTRSCR     0x94
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#define MPC8544_GUTS_ADDR_PVR         0xA0
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#define MPC8544_GUTS_ADDR_SVR         0xA4
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#define MPC8544_GUTS_ADDR_RSTCR       0xB0
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#define MPC8544_GUTS_ADDR_IOVSELSR    0xC0
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#define MPC8544_GUTS_ADDR_DDRCSR      0xB20
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#define MPC8544_GUTS_ADDR_DDRCDR      0xB24
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#define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28
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#define MPC8544_GUTS_ADDR_CLKOCR      0xE00
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#define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04
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#define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10
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#define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18
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#define TYPE_MPC8544_GUTS "mpc8544-guts"
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OBJECT_DECLARE_SIMPLE_TYPE(GutsState, MPC8544_GUTS)
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struct GutsState {
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    /*< private >*/
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    SysBusDevice parent_obj;
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    /*< public >*/
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    MemoryRegion iomem;
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};
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static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
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                                  unsigned size)
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{
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    uint32_t value = 0;
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    CPUPPCState *env = cpu_env(current_cpu);
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    addr &= MPC8544_GUTS_MMIO_SIZE - 1;
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    switch (addr) {
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    case MPC8544_GUTS_ADDR_PORPLLSR:
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        value = FIELD_DP32(value, GUTS_PORPLLSR, E500_1_RATIO, 6); /* 3:1 */
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        value = FIELD_DP32(value, GUTS_PORPLLSR, E500_0_RATIO, 6); /* 3:1 */
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        value = FIELD_DP32(value, GUTS_PORPLLSR, DDR_RATIO, 12); /* 12:1 */
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        value = FIELD_DP32(value, GUTS_PORPLLSR, PLAT_RATIO, 6); /* 6:1 */
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        break;
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    case MPC8544_GUTS_ADDR_PVR:
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        value = env->spr[SPR_PVR];
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        break;
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    case MPC8544_GUTS_ADDR_SVR:
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        value = env->spr[SPR_E500_SVR];
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Unknown register 0x%" HWADDR_PRIx "\n",
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                      __func__, addr);
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        break;
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    }
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    return value;
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}
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static void mpc8544_guts_write(void *opaque, hwaddr addr,
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                               uint64_t value, unsigned size)
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{
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    addr &= MPC8544_GUTS_MMIO_SIZE - 1;
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    switch (addr) {
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    case MPC8544_GUTS_ADDR_RSTCR:
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        if (value & MPC8544_GUTS_RSTCR_RESET) {
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            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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        }
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown register 0x%" HWADDR_PRIx
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                       " = 0x%" PRIx64 "\n", __func__, addr, value);
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        break;
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    }
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}
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static const MemoryRegionOps mpc8544_guts_ops = {
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    .read = mpc8544_guts_read,
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    .write = mpc8544_guts_write,
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    .endianness = DEVICE_BIG_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static void mpc8544_guts_initfn(Object *obj)
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{
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    SysBusDevice *d = SYS_BUS_DEVICE(obj);
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    GutsState *s = MPC8544_GUTS(obj);
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    memory_region_init_io(&s->iomem, OBJECT(s), &mpc8544_guts_ops, s,
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                          "mpc8544.guts", MPC8544_GUTS_MMIO_SIZE);
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    sysbus_init_mmio(d, &s->iomem);
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}
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static const TypeInfo mpc8544_guts_types[] = {
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    {
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        .name          = TYPE_MPC8544_GUTS,
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        .parent        = TYPE_SYS_BUS_DEVICE,
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        .instance_size = sizeof(GutsState),
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        .instance_init = mpc8544_guts_initfn,
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    },
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};
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DEFINE_TYPES(mpc8544_guts_types)
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