- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
 - Add '-d invalid_mem' logging option (Zoltan)
 - Create QOM containers explicitly (Peter)
 - Rename sysemu/ -> system/ (Philippe)
 - Re-orderning of include/exec/ headers (Philippe)
   Move a lot of declarations from these legacy mixed bag headers:
     . "exec/cpu-all.h"
     . "exec/cpu-common.h"
     . "exec/cpu-defs.h"
     . "exec/exec-all.h"
     . "exec/translate-all"
   to these more specific ones:
     . "exec/page-protection.h"
     . "exec/translation-block.h"
     . "user/cpu_loop.h"
     . "user/guest-host.h"
     . "user/page-protection.h"
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Merge tag 'exec-20241220' of https://github.com/philmd/qemu into staging
Accel & Exec patch queue
- Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander)
- Add '-d invalid_mem' logging option (Zoltan)
- Create QOM containers explicitly (Peter)
- Rename sysemu/ -> system/ (Philippe)
- Re-orderning of include/exec/ headers (Philippe)
  Move a lot of declarations from these legacy mixed bag headers:
    . "exec/cpu-all.h"
    . "exec/cpu-common.h"
    . "exec/cpu-defs.h"
    . "exec/exec-all.h"
    . "exec/translate-all"
  to these more specific ones:
    . "exec/page-protection.h"
    . "exec/translation-block.h"
    . "user/cpu_loop.h"
    . "user/guest-host.h"
    . "user/page-protection.h"
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 # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST
 # gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
 # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
 # gpg: WARNING: This key is not certified with a trusted signature!
 # gpg:          There is no indication that the signature belongs to the owner.
 # Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE
* tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits)
  util/qemu-timer: fix indentation
  meson: Do not define CONFIG_DEVICES on user emulation
  system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header
  system/numa: Remove unnecessary 'exec/cpu-common.h' header
  hw/xen: Remove unnecessary 'exec/cpu-common.h' header
  target/mips: Drop left-over comment about Jazz machine
  target/mips: Remove tswap() calls in semihosting uhi_fstat_cb()
  target/xtensa: Remove tswap() calls in semihosting simcall() helper
  accel/tcg: Un-inline translator_is_same_page()
  accel/tcg: Include missing 'exec/translation-block.h' header
  accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h'
  accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h'
  qemu/coroutine: Include missing 'qemu/atomic.h' header
  exec/translation-block: Include missing 'qemu/atomic.h' header
  accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h'
  exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined
  target/sparc: Move sparc_restore_state_to_opc() to cpu.c
  target/sparc: Uninline cpu_get_tb_cpu_state()
  target/loongarch: Declare loongarch_cpu_dump_state() locally
  user: Move various declarations out of 'exec/exec-all.h'
  ...
Conflicts:
	hw/char/riscv_htif.c
	hw/intc/riscv_aplic.c
	target/s390x/cpu.c
	Apply sysemu header path changes to not in the pull request.
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
		
	
			
		
			
				
	
	
		
			134 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			134 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * QEMU IDE Emulation: ISA Bus support.
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 * Copyright (c) 2006 Openedhand Ltd.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/isa/isa.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "system/dma.h"
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#include "hw/ide/isa.h"
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#include "qom/object.h"
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#include "ide-internal.h"
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/***********************************************************/
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/* ISA IDE definitions */
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struct ISAIDEState {
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    ISADevice parent_obj;
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    IDEBus    bus;
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    uint32_t  iobase;
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    uint32_t  iobase2;
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    uint32_t  irqnum;
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};
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static void isa_ide_reset(DeviceState *d)
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{
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    ISAIDEState *s = ISA_IDE(d);
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    ide_bus_reset(&s->bus);
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}
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static const VMStateDescription vmstate_ide_isa = {
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    .name = "isa-ide",
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    .version_id = 3,
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    .minimum_version_id = 0,
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    .fields = (const VMStateField[]) {
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        VMSTATE_IDE_BUS(bus, ISAIDEState),
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        VMSTATE_IDE_DRIVES(bus.ifs, ISAIDEState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void isa_ide_realizefn(DeviceState *dev, Error **errp)
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{
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    ISADevice *isadev = ISA_DEVICE(dev);
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    ISAIDEState *s = ISA_IDE(dev);
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    ide_bus_init(&s->bus, sizeof(s->bus), dev, 0, 2);
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    ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
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    ide_bus_init_output_irq(&s->bus, isa_get_irq(isadev, s->irqnum));
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    vmstate_register_any(VMSTATE_IF(dev), &vmstate_ide_isa, s);
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    ide_bus_register_restart_cb(&s->bus);
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}
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ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int irqnum,
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                        DriveInfo *hd0, DriveInfo *hd1)
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{
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    DeviceState *dev;
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    ISADevice *isadev;
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    ISAIDEState *s;
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    isadev = isa_new(TYPE_ISA_IDE);
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    dev = DEVICE(isadev);
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    qdev_prop_set_uint32(dev, "iobase",  iobase);
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    qdev_prop_set_uint32(dev, "iobase2", iobase2);
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    qdev_prop_set_uint32(dev, "irq",     irqnum);
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    isa_realize_and_unref(isadev, bus, &error_fatal);
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    s = ISA_IDE(dev);
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    if (hd0) {
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        ide_bus_create_drive(&s->bus, 0, hd0);
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    }
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    if (hd1) {
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        ide_bus_create_drive(&s->bus, 1, hd1);
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    }
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    return isadev;
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}
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static const Property isa_ide_properties[] = {
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    DEFINE_PROP_UINT32("iobase",  ISAIDEState, iobase,  0x1f0),
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    DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
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    DEFINE_PROP_UINT32("irq",     ISAIDEState, irqnum,  14),
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};
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static void isa_ide_class_initfn(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = isa_ide_realizefn;
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    dc->fw_name = "ide";
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    device_class_set_legacy_reset(dc, isa_ide_reset);
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    device_class_set_props(dc, isa_ide_properties);
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    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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}
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static const TypeInfo isa_ide_info = {
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    .name          = TYPE_ISA_IDE,
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    .parent        = TYPE_ISA_DEVICE,
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    .instance_size = sizeof(ISAIDEState),
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    .class_init    = isa_ide_class_initfn,
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};
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static void isa_ide_register_types(void)
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{
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    type_register_static(&isa_ide_info);
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}
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type_init(isa_ide_register_types)
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