FRET-qemu/target-arm
Alex Bennée dbb1fb277c target-arm: A64: fix TLB flush instructions
According to the ARM ARM we weren't correctly flushing the TLB entries
where bits 63:56 didn't match bit 55 of the virtual address. This
exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to
12 for aarch64.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04 14:41:56 +01:00
..
2014-06-05 16:10:33 +02:00
2014-08-04 14:41:54 +01:00
2014-08-04 14:41:55 +01:00
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