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		a8259b5323
		
	
	
	
	
		
			
			We were accidently passing RISCVHartArrayState by value instead of pointer. The type is 824 bytes long so let's correct that and pass it by pointer instead. Fixes: Coverity CID 1438099 Fixes: Coverity CID 1438100 Fixes: Coverity CID 1438101 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
		
			
				
	
	
		
			56 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			56 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * QEMU RISC-V Boot Helper
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|  *
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|  * Copyright (c) 2017 SiFive, Inc.
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|  * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify it
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|  * under the terms and conditions of the GNU General Public License,
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|  * version 2 or later, as published by the Free Software Foundation.
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|  *
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|  * This program is distributed in the hope it will be useful, but WITHOUT
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|  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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|  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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|  * more details.
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|  *
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|  * You should have received a copy of the GNU General Public License along with
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|  * this program.  If not, see <http://www.gnu.org/licenses/>.
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|  */
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| 
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| #ifndef RISCV_BOOT_H
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| #define RISCV_BOOT_H
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| 
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| #include "exec/cpu-defs.h"
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| #include "hw/loader.h"
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| #include "hw/riscv/riscv_hart.h"
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| 
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| bool riscv_is_32bit(RISCVHartArrayState *harts);
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| 
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| target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
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|                                           target_ulong firmware_end_addr);
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| target_ulong riscv_find_and_load_firmware(MachineState *machine,
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|                                           const char *default_machine_firmware,
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|                                           hwaddr firmware_load_addr,
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|                                           symbol_fn_t sym_cb);
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| char *riscv_find_firmware(const char *firmware_filename);
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| target_ulong riscv_load_firmware(const char *firmware_filename,
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|                                  hwaddr firmware_load_addr,
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|                                  symbol_fn_t sym_cb);
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| target_ulong riscv_load_kernel(const char *kernel_filename,
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|                                target_ulong firmware_end_addr,
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|                                symbol_fn_t sym_cb);
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| hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
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|                          uint64_t kernel_entry, hwaddr *start);
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| uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
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| void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
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|                                hwaddr saddr,
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|                                hwaddr rom_base, hwaddr rom_size,
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|                                uint64_t kernel_entry,
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|                                uint32_t fdt_load_addr, void *fdt);
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| void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
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|                                   hwaddr rom_size,
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|                                   uint32_t reset_vec_size,
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|                                   uint64_t kernel_entry);
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| 
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| #endif /* RISCV_BOOT_H */
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