Peer Adelt 550929dd46 target-tricore: Added new MOV instruction variant ...

Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].

[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

2017-01-11 14:37:15 +01:00

..

alpha

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

arm

target-arm: Add VBAR support to ARM1176 CPUs

2016-12-27 14:59:30 +00:00

cris

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

i386

x86: implement la57 paging mode

2016-12-22 16:01:04 +01:00

lm32

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

m68k

target-m68k: free TCG variables that are not

2016-12-27 18:28:40 +01:00

microblaze

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

mips

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

moxie

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

openrisc

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

ppc

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

s390x

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

sh4

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

sparc

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

tilegx

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

tricore

target-tricore: Added new MOV instruction variant

2017-01-11 14:37:15 +01:00

unicore32

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00

xtensa

Move target-* CPU file into a target/ folder

2016-12-20 21:52:12 +01:00