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FRET-qemu/target/riscv
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Marc-André Lureau 4f67d30b5e qdev: set properties with device_class_set_props() 
The following patch will need to handle properties registration during
class_init time. Let's use a device_class_set_props() setter.

spatch --macro-file scripts/cocci-macro-file.h  --sp-file
./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place
--dir .

@@
typedef DeviceClass;
DeviceClass *d;
expression val;
@@
- d->props = val
+ device_class_set_props(d, val)

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-01-24 20:59:15 +01:00
..
insn_trans
tcg: TCGMemOp is now accelerator independent MemOp
2019-09-03 08:30:38 -07:00
cpu_bits.h
target/riscv: Update the Hypervisor CSRs to v0.4
2019-09-17 08:42:43 -07:00
cpu_helper.c
tcg: Search includes from the project root source directory
2020-01-15 15:13:10 -10:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu-param.h
tcg: Split out target/arch/cpu-param.h
2019-06-10 07:03:34 -07:00
cpu.c
qdev: set properties with device_class_set_props()
2020-01-24 20:59:15 +01:00
cpu.h
target/riscv: Remove atomic accesses to MIP CSR
2019-11-14 09:53:28 -08:00
csr.c
target/riscv: Remove atomic accesses to MIP CSR
2019-11-14 09:53:28 -08:00
fpu_helper.c
target/riscv: rationalise softfloat includes
2019-08-19 12:07:13 +01:00
gdbstub.c
target/riscv: Make the priv register writable by GDB
2019-10-28 07:47:29 -07:00
helper.h
RISC-V CPU Helpers
2018-03-07 08:30:28 +13:00
insn16-32.decode
target/riscv: Split RVC32 and RVC64 insns into separate files
2019-05-24 12:09:22 -07:00
insn16-64.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn16.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn32-64.decode
target/riscv: Convert RV64D insns to decodetree
2019-03-13 10:34:06 +01:00
insn32.decode
target/riscv: Name the argument sets for all of insn32 formats
2019-05-24 12:09:22 -07:00
instmap.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
Makefile.objs
riscv: hmp: Add a command to show virtual memory mappings
2019-09-17 08:42:43 -07:00
monitor.c
riscv: hmp: Add a command to show virtual memory mappings
2019-09-17 08:42:43 -07:00
op_helper.c
target/riscv: Use env_cpu, env_archcpu
2019-06-10 07:03:42 -07:00
pmp.c
target/riscv: PMP violation due to wrong size parameter
2019-10-28 08:46:33 -07:00
pmp.h
RISC-V: Check for the effective memory privilege mode during PMP checks
2019-06-23 23:44:41 -07:00
trace-events
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
2019-09-17 08:42:42 -07:00
translate.c
tcg: Search includes from the project root source directory
2020-01-15 15:13:10 -10:00