c7f9dd5465
Adding defines to handle signed 64-bit and unsigned 128-bit quantities in memory accesses. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-3-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* Constants for memory operations
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*
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* Authors:
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* Richard Henderson <rth@twiddle.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef MEMOP_H
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#define MEMOP_H
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#include "qemu/host-utils.h"
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typedef enum MemOp {
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MO_8 = 0,
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MO_16 = 1,
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MO_32 = 2,
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MO_64 = 3,
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MO_128 = 4,
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MO_256 = 5,
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MO_512 = 6,
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MO_1024 = 7,
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MO_SIZE = 0x07, /* Mask for the above. */
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MO_SIGN = 0x08, /* Sign-extended, otherwise zero-extended. */
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MO_BSWAP = 0x10, /* Host reverse endian. */
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#ifdef HOST_WORDS_BIGENDIAN
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MO_LE = MO_BSWAP,
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MO_BE = 0,
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#else
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MO_LE = 0,
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MO_BE = MO_BSWAP,
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#endif
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#ifdef NEED_CPU_H
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#ifdef TARGET_WORDS_BIGENDIAN
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MO_TE = MO_BE,
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#else
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MO_TE = MO_LE,
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#endif
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#endif
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/*
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* MO_UNALN accesses are never checked for alignment.
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* MO_ALIGN accesses will result in a call to the CPU's
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* do_unaligned_access hook if the guest address is not aligned.
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* The default depends on whether the target CPU defines
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* TARGET_ALIGNED_ONLY.
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*
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* Some architectures (e.g. ARMv8) need the address which is aligned
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* to a size more than the size of the memory access.
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* Some architectures (e.g. SPARCv9) need an address which is aligned,
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* but less strictly than the natural alignment.
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*
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* MO_ALIGN supposes the alignment size is the size of a memory access.
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*
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* There are three options:
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* - unaligned access permitted (MO_UNALN).
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* - an alignment to the size of an access (MO_ALIGN);
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* - an alignment to a specified size, which may be more or less than
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* the access size (MO_ALIGN_x where 'x' is a size in bytes);
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*/
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MO_ASHIFT = 5,
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MO_AMASK = 0x7 << MO_ASHIFT,
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#ifdef NEED_CPU_H
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#ifdef TARGET_ALIGNED_ONLY
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MO_ALIGN = 0,
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MO_UNALN = MO_AMASK,
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#else
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MO_ALIGN = MO_AMASK,
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MO_UNALN = 0,
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#endif
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#endif
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MO_ALIGN_2 = 1 << MO_ASHIFT,
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MO_ALIGN_4 = 2 << MO_ASHIFT,
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MO_ALIGN_8 = 3 << MO_ASHIFT,
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MO_ALIGN_16 = 4 << MO_ASHIFT,
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MO_ALIGN_32 = 5 << MO_ASHIFT,
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MO_ALIGN_64 = 6 << MO_ASHIFT,
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/* Combinations of the above, for ease of use. */
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MO_UB = MO_8,
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MO_UW = MO_16,
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MO_UL = MO_32,
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MO_UQ = MO_64,
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MO_UO = MO_128,
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MO_SB = MO_SIGN | MO_8,
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MO_SW = MO_SIGN | MO_16,
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MO_SL = MO_SIGN | MO_32,
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MO_SQ = MO_SIGN | MO_64,
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MO_SO = MO_SIGN | MO_128,
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MO_LEUW = MO_LE | MO_UW,
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MO_LEUL = MO_LE | MO_UL,
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MO_LEUQ = MO_LE | MO_UQ,
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MO_LESW = MO_LE | MO_SW,
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MO_LESL = MO_LE | MO_SL,
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MO_LESQ = MO_LE | MO_SQ,
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MO_BEUW = MO_BE | MO_UW,
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MO_BEUL = MO_BE | MO_UL,
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MO_BEUQ = MO_BE | MO_UQ,
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MO_BESW = MO_BE | MO_SW,
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MO_BESL = MO_BE | MO_SL,
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MO_BESQ = MO_BE | MO_SQ,
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#ifdef NEED_CPU_H
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MO_TEUW = MO_TE | MO_UW,
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MO_TEUL = MO_TE | MO_UL,
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MO_TEUQ = MO_TE | MO_UQ,
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MO_TEUO = MO_TE | MO_UO,
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MO_TESW = MO_TE | MO_SW,
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MO_TESL = MO_TE | MO_SL,
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MO_TESQ = MO_TE | MO_SQ,
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#endif
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MO_SSIZE = MO_SIZE | MO_SIGN,
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} MemOp;
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/* MemOp to size in bytes. */
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static inline unsigned memop_size(MemOp op)
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{
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return 1 << (op & MO_SIZE);
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}
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/* Size in bytes to MemOp. */
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static inline MemOp size_memop(unsigned size)
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{
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#ifdef CONFIG_DEBUG_TCG
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/* Power of 2 up to 8. */
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assert((size & (size - 1)) == 0 && size >= 1 && size <= 8);
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#endif
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return ctz32(size);
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}
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/* Big endianness from MemOp. */
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static inline bool memop_big_endian(MemOp op)
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{
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return (op & MO_BSWAP) == MO_BE;
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}
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#endif
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