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FRET-qemu/hw/pci-bridge
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Jonathan Cameron 7e33517fdd hw/pci-bridge/cxl_root_port: Wire up MSI 
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
2023-03-07 12:39:00 -05:00
..
cxl_downstream.c
hw/pci-bridge/cxl_downstream: Fix type naming mismatch
2023-03-02 19:13:52 -05:00
cxl_root_port.c
hw/pci-bridge/cxl_root_port: Wire up MSI
2023-03-07 12:39:00 -05:00
cxl_upstream.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
gen_pcie_root_port.c
pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-cap
2023-01-28 06:21:29 -05:00
i82801b11.c
hw: Move ich9.h to southbridge/
2023-02-27 22:29:01 +01:00
ioh3420.c
Include migration/vmstate.h less
2019-08-16 13:31:52 +02:00
Kconfig
hw/cxl/rp: Add a root port
2022-05-13 06:13:36 -04:00
meson.build
remove DEC 21154 PCI bridge
2022-12-21 07:32:24 -05:00
pci_bridge_dev.c
pci_bridge: remove whitespace
2023-01-28 06:21:29 -05:00
pci_expander_bridge_stubs.c
pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.
2022-06-09 19:32:49 -04:00
pci_expander_bridge.c
bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx
2023-01-18 11:14:34 +01:00
pcie_pci_bridge.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
pcie_root_port.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
simba.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
xio3130_downstream.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00
xio3130_upstream.c
pci: drop redundant PCIDeviceClass::is_bridge field
2022-12-21 07:32:24 -05:00