Bin Meng 4921a0ce86 hw/riscv: Move sifive_gpio model to hw/gpio
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.

Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09 15:54:19 -07:00
..
2020-08-28 15:14:40 +01:00
2020-08-27 14:04:55 -04:00
2019-08-16 13:31:53 +02:00
2020-08-27 14:04:54 -04:00
2020-09-01 11:08:57 +02:00
2020-08-27 14:04:54 -04:00
2020-08-27 14:04:54 -04:00
2019-08-16 13:31:53 +02:00
2020-09-08 10:08:42 +10:00
2019-06-12 13:20:21 +02:00
2019-08-16 13:31:52 +02:00
2019-06-12 13:20:21 +02:00
2020-06-22 18:37:12 +02:00
2020-05-15 07:08:14 +02:00
2020-09-09 15:54:18 -07:00
2019-08-16 13:31:53 +02:00
2019-08-16 13:31:52 +02:00
2019-08-16 13:31:52 +02:00
2020-08-19 10:45:48 -04:00
2018-12-11 15:45:22 -02:00
2019-08-16 13:31:52 +02:00
2019-08-16 13:31:53 +02:00
2019-06-12 13:20:21 +02:00
2020-06-15 22:05:28 +02:00