152f0bf0c9
Add a model of the Xilinx ZynqMP CRF. At the moment this is mostly a stub model. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
212 lines
7.2 KiB
C
212 lines
7.2 KiB
C
/*
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* QEMU model of the CRF - Clock Reset FPD.
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*
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* Copyright (c) 2022 Xilinx Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*/
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#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
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#define HW_MISC_XLNX_ZYNQMP_CRF_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
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REG32(ERR_CTRL, 0x0)
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FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
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REG32(IR_STATUS, 0x4)
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FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_MASK, 0x8)
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FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_ENABLE, 0xc)
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FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
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REG32(IR_DISABLE, 0x10)
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FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
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REG32(CRF_WPROT, 0x1c)
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FIELD(CRF_WPROT, ACTIVE, 0, 1)
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REG32(APLL_CTRL, 0x20)
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FIELD(APLL_CTRL, POST_SRC, 24, 3)
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FIELD(APLL_CTRL, PRE_SRC, 20, 3)
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FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(APLL_CTRL, DIV2, 16, 1)
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FIELD(APLL_CTRL, FBDIV, 8, 7)
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FIELD(APLL_CTRL, BYPASS, 3, 1)
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FIELD(APLL_CTRL, RESET, 0, 1)
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REG32(APLL_CFG, 0x24)
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FIELD(APLL_CFG, LOCK_DLY, 25, 7)
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FIELD(APLL_CFG, LOCK_CNT, 13, 10)
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FIELD(APLL_CFG, LFHF, 10, 2)
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FIELD(APLL_CFG, CP, 5, 4)
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FIELD(APLL_CFG, RES, 0, 4)
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REG32(APLL_FRAC_CFG, 0x28)
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FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(APLL_FRAC_CFG, SEED, 22, 3)
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FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(APLL_FRAC_CFG, DATA, 0, 16)
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REG32(DPLL_CTRL, 0x2c)
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FIELD(DPLL_CTRL, POST_SRC, 24, 3)
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FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(DPLL_CTRL, DIV2, 16, 1)
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FIELD(DPLL_CTRL, FBDIV, 8, 7)
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FIELD(DPLL_CTRL, BYPASS, 3, 1)
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FIELD(DPLL_CTRL, RESET, 0, 1)
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REG32(DPLL_CFG, 0x30)
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FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(DPLL_CFG, LFHF, 10, 2)
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FIELD(DPLL_CFG, CP, 5, 4)
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FIELD(DPLL_CFG, RES, 0, 4)
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REG32(DPLL_FRAC_CFG, 0x34)
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FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
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FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
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REG32(VPLL_CTRL, 0x38)
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FIELD(VPLL_CTRL, POST_SRC, 24, 3)
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FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
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FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
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FIELD(VPLL_CTRL, DIV2, 16, 1)
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FIELD(VPLL_CTRL, FBDIV, 8, 7)
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FIELD(VPLL_CTRL, BYPASS, 3, 1)
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FIELD(VPLL_CTRL, RESET, 0, 1)
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REG32(VPLL_CFG, 0x3c)
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FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
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FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
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FIELD(VPLL_CFG, LFHF, 10, 2)
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FIELD(VPLL_CFG, CP, 5, 4)
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FIELD(VPLL_CFG, RES, 0, 4)
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REG32(VPLL_FRAC_CFG, 0x40)
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FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
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FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
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FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
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FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
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FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
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REG32(PLL_STATUS, 0x44)
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FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
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FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
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FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
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FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
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FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
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FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
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REG32(APLL_TO_LPD_CTRL, 0x48)
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FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
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REG32(DPLL_TO_LPD_CTRL, 0x4c)
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FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
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REG32(VPLL_TO_LPD_CTRL, 0x50)
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FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
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REG32(ACPU_CTRL, 0x60)
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FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
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FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
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FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
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FIELD(ACPU_CTRL, SRCSEL, 0, 3)
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REG32(DBG_TRACE_CTRL, 0x64)
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FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
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FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
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FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
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REG32(DBG_FPD_CTRL, 0x68)
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FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
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FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
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FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
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REG32(DP_VIDEO_REF_CTRL, 0x70)
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FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
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FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
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FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
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REG32(DP_AUDIO_REF_CTRL, 0x74)
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FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
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FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
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FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
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REG32(DP_STC_REF_CTRL, 0x7c)
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FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
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FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
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FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
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REG32(DDR_CTRL, 0x80)
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FIELD(DDR_CTRL, CLKACT, 24, 1)
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FIELD(DDR_CTRL, DIVISOR0, 8, 6)
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FIELD(DDR_CTRL, SRCSEL, 0, 3)
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REG32(GPU_REF_CTRL, 0x84)
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FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
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FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
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FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
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FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
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REG32(SATA_REF_CTRL, 0xa0)
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FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
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FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
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REG32(PCIE_REF_CTRL, 0xb4)
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FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
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FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
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REG32(GDMA_REF_CTRL, 0xb8)
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FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
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FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
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REG32(DPDMA_REF_CTRL, 0xbc)
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FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
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FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
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FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
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REG32(TOPSW_MAIN_CTRL, 0xc0)
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FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
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FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
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FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
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REG32(TOPSW_LSBUS_CTRL, 0xc4)
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FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
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FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
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FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
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REG32(DBG_TSTMP_CTRL, 0xf8)
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FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
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FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
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REG32(RST_FPD_TOP, 0x100)
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FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
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FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
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FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
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FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
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FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
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FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
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FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
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FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
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FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
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FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
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FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
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FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
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FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
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FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
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FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
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FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
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FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
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REG32(RST_FPD_APU, 0x104)
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FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
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FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
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FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
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FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
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FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
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FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
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FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
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FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
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FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
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REG32(RST_DDR_SS, 0x108)
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FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
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FIELD(RST_DDR_SS, APM_RESET, 2, 1)
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#define CRF_R_MAX (R_RST_DDR_SS + 1)
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struct XlnxZynqMPCRF {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq_ir;
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RegisterInfoArray *reg_array;
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uint32_t regs[CRF_R_MAX];
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RegisterInfo regs_info[CRF_R_MAX];
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};
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#endif
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