Make the Aspeed HACE module use the new qcrypto accumulative hashing functions when in scatter-gather accumulative mode. A hash context will maintain a "running-hash" as each scatter-gather chunk is received. Previously each scatter-gather "chunk" was cached so the hash could be computed once the final chunk was received. However, the cache was a shallow copy, so once the guest overwrote the memory provided to HACE the final hash would not be correct. Possibly related to: https://gitlab.com/qemu-project/qemu/-/issues/1121 Buglink: https://github.com/openbmc/qemu/issues/36 Signed-off-by: Alejandro Zeise <alejandro.zeise@seagate.com> [ clg: - Checkpatch fixes - Reworked qcrypto_hash*() error reports in do_hash_operation() ] Signed-off-by: Cédric Le Goater <clg@redhat.com> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au>
		
			
				
	
	
		
			55 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			55 lines
		
	
	
		
			1.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * ASPEED Hash and Crypto Engine
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 *
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 * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates
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 * Copyright (C) 2021 IBM Corp.
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 *
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 */
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#ifndef ASPEED_HACE_H
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#define ASPEED_HACE_H
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#include "hw/sysbus.h"
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#include "crypto/hash.h"
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#define TYPE_ASPEED_HACE "aspeed.hace"
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#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
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#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
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#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
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#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
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OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
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#define ASPEED_HACE_NR_REGS (0x64 >> 2)
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#define ASPEED_HACE_MAX_SG  256 /* max number of entries */
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struct AspeedHACEState {
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    SysBusDevice parent;
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    MemoryRegion iomem;
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    qemu_irq irq;
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    struct iovec iov_cache[ASPEED_HACE_MAX_SG];
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    uint32_t regs[ASPEED_HACE_NR_REGS];
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    uint32_t total_req_len;
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    uint32_t iov_count;
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    MemoryRegion *dram_mr;
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    AddressSpace dram_as;
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    QCryptoHash *hash_ctx;
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};
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struct AspeedHACEClass {
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    SysBusDeviceClass parent_class;
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    uint32_t src_mask;
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    uint32_t dest_mask;
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    uint32_t key_mask;
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    uint32_t hash_mask;
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};
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#endif /* ASPEED_HACE_H */
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