de531a6bd4
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
425 lines
13 KiB
C
425 lines
13 KiB
C
/*
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* Nuvoton NPCM7xx General Purpose Input / Output (GPIO)
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/gpio/npcm7xx_gpio.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "trace.h"
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/* 32-bit register indices. */
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enum NPCM7xxGPIORegister {
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NPCM7XX_GPIO_TLOCK1,
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NPCM7XX_GPIO_DIN,
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NPCM7XX_GPIO_POL,
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NPCM7XX_GPIO_DOUT,
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NPCM7XX_GPIO_OE,
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NPCM7XX_GPIO_OTYP,
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NPCM7XX_GPIO_MP,
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NPCM7XX_GPIO_PU,
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NPCM7XX_GPIO_PD,
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NPCM7XX_GPIO_DBNC,
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NPCM7XX_GPIO_EVTYP,
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NPCM7XX_GPIO_EVBE,
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NPCM7XX_GPIO_OBL0,
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NPCM7XX_GPIO_OBL1,
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NPCM7XX_GPIO_OBL2,
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NPCM7XX_GPIO_OBL3,
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NPCM7XX_GPIO_EVEN,
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NPCM7XX_GPIO_EVENS,
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NPCM7XX_GPIO_EVENC,
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NPCM7XX_GPIO_EVST,
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NPCM7XX_GPIO_SPLCK,
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NPCM7XX_GPIO_MPLCK,
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NPCM7XX_GPIO_IEM,
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NPCM7XX_GPIO_OSRC,
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NPCM7XX_GPIO_ODSC,
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NPCM7XX_GPIO_DOS = 0x68 / sizeof(uint32_t),
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NPCM7XX_GPIO_DOC,
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NPCM7XX_GPIO_OES,
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NPCM7XX_GPIO_OEC,
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NPCM7XX_GPIO_TLOCK2 = 0x7c / sizeof(uint32_t),
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NPCM7XX_GPIO_REGS_END,
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};
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#define NPCM7XX_GPIO_REGS_SIZE (4 * KiB)
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#define NPCM7XX_GPIO_LOCK_MAGIC1 (0xc0defa73)
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#define NPCM7XX_GPIO_LOCK_MAGIC2 (0xc0de1248)
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static void npcm7xx_gpio_update_events(NPCM7xxGPIOState *s, uint32_t din_diff)
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{
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uint32_t din_new = s->regs[NPCM7XX_GPIO_DIN];
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/* Trigger on high level */
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s->regs[NPCM7XX_GPIO_EVST] |= din_new & ~s->regs[NPCM7XX_GPIO_EVTYP];
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/* Trigger on both edges */
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s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & s->regs[NPCM7XX_GPIO_EVTYP]
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& s->regs[NPCM7XX_GPIO_EVBE]);
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/* Trigger on rising edge */
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s->regs[NPCM7XX_GPIO_EVST] |= (din_diff & din_new
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& s->regs[NPCM7XX_GPIO_EVTYP]);
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trace_npcm7xx_gpio_update_events(DEVICE(s)->canonical_path,
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s->regs[NPCM7XX_GPIO_EVST],
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s->regs[NPCM7XX_GPIO_EVEN]);
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qemu_set_irq(s->irq, !!(s->regs[NPCM7XX_GPIO_EVST]
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& s->regs[NPCM7XX_GPIO_EVEN]));
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}
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static void npcm7xx_gpio_update_pins(NPCM7xxGPIOState *s, uint32_t diff)
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{
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uint32_t drive_en;
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uint32_t drive_lvl;
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uint32_t not_driven;
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uint32_t undefined;
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uint32_t pin_diff;
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uint32_t din_old;
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/* Calculate level of each pin driven by GPIO controller. */
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drive_lvl = s->regs[NPCM7XX_GPIO_DOUT] ^ s->regs[NPCM7XX_GPIO_POL];
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/* If OTYP=1, only drive low (open drain) */
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drive_en = s->regs[NPCM7XX_GPIO_OE] & ~(s->regs[NPCM7XX_GPIO_OTYP]
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& drive_lvl);
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/*
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* If a pin is driven to opposite levels by the GPIO controller and the
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* external driver, the result is undefined.
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*/
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undefined = drive_en & s->ext_driven & (drive_lvl ^ s->ext_level);
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if (undefined) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: pins have multiple drivers: 0x%" PRIx32 "\n",
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DEVICE(s)->canonical_path, undefined);
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}
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not_driven = ~(drive_en | s->ext_driven);
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pin_diff = s->pin_level;
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/* Set pins to externally driven level. */
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s->pin_level = s->ext_level & s->ext_driven;
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/* Set internally driven pins, ignoring any conflicts. */
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s->pin_level |= drive_lvl & drive_en;
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/* Pull up undriven pins with internal pull-up enabled. */
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s->pin_level |= not_driven & s->regs[NPCM7XX_GPIO_PU];
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/* Pins not driven, pulled up or pulled down are undefined */
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undefined |= not_driven & ~(s->regs[NPCM7XX_GPIO_PU]
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| s->regs[NPCM7XX_GPIO_PD]);
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/* If any pins changed state, update the outgoing GPIOs. */
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pin_diff ^= s->pin_level;
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pin_diff |= undefined & diff;
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if (pin_diff) {
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int i;
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for (i = 0; i < NPCM7XX_GPIO_NR_PINS; i++) {
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uint32_t mask = BIT(i);
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if (pin_diff & mask) {
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int level = (undefined & mask) ? -1 : !!(s->pin_level & mask);
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trace_npcm7xx_gpio_set_output(DEVICE(s)->canonical_path,
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i, level);
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qemu_set_irq(s->output[i], level);
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}
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}
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}
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/* Calculate new value of DIN after masking and polarity setting. */
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din_old = s->regs[NPCM7XX_GPIO_DIN];
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s->regs[NPCM7XX_GPIO_DIN] = ((s->pin_level & s->regs[NPCM7XX_GPIO_IEM])
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^ s->regs[NPCM7XX_GPIO_POL]);
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/* See if any new events triggered because of all this. */
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npcm7xx_gpio_update_events(s, din_old ^ s->regs[NPCM7XX_GPIO_DIN]);
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}
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static bool npcm7xx_gpio_is_locked(NPCM7xxGPIOState *s)
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{
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return s->regs[NPCM7XX_GPIO_TLOCK1] == 1;
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}
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static uint64_t npcm7xx_gpio_regs_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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hwaddr reg = addr / sizeof(uint32_t);
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NPCM7xxGPIOState *s = opaque;
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uint64_t value = 0;
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switch (reg) {
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case NPCM7XX_GPIO_TLOCK1 ... NPCM7XX_GPIO_EVEN:
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case NPCM7XX_GPIO_EVST ... NPCM7XX_GPIO_ODSC:
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value = s->regs[reg];
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break;
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case NPCM7XX_GPIO_EVENS ... NPCM7XX_GPIO_EVENC:
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case NPCM7XX_GPIO_DOS ... NPCM7XX_GPIO_TLOCK2:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: read from write-only register 0x%" HWADDR_PRIx "\n",
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DEVICE(s)->canonical_path, addr);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
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DEVICE(s)->canonical_path, addr);
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break;
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}
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trace_npcm7xx_gpio_read(DEVICE(s)->canonical_path, addr, value);
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return value;
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}
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static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
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unsigned int size)
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{
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hwaddr reg = addr / sizeof(uint32_t);
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NPCM7xxGPIOState *s = opaque;
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uint32_t value = v;
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uint32_t diff;
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trace_npcm7xx_gpio_write(DEVICE(s)->canonical_path, addr, v);
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if (npcm7xx_gpio_is_locked(s)) {
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switch (reg) {
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case NPCM7XX_GPIO_TLOCK1:
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if (s->regs[NPCM7XX_GPIO_TLOCK2] == NPCM7XX_GPIO_LOCK_MAGIC2 &&
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value == NPCM7XX_GPIO_LOCK_MAGIC1) {
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s->regs[NPCM7XX_GPIO_TLOCK1] = 0;
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s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
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}
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break;
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case NPCM7XX_GPIO_TLOCK2:
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s->regs[reg] = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to locked register @ 0x%" HWADDR_PRIx "\n",
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DEVICE(s)->canonical_path, addr);
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break;
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}
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return;
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}
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diff = s->regs[reg] ^ value;
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switch (reg) {
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case NPCM7XX_GPIO_TLOCK1:
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case NPCM7XX_GPIO_TLOCK2:
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s->regs[NPCM7XX_GPIO_TLOCK1] = 1;
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s->regs[NPCM7XX_GPIO_TLOCK2] = 0;
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break;
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case NPCM7XX_GPIO_DIN:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
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DEVICE(s)->canonical_path, addr);
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break;
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case NPCM7XX_GPIO_POL:
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case NPCM7XX_GPIO_DOUT:
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case NPCM7XX_GPIO_OE:
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case NPCM7XX_GPIO_OTYP:
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case NPCM7XX_GPIO_PU:
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case NPCM7XX_GPIO_PD:
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case NPCM7XX_GPIO_IEM:
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s->regs[reg] = value;
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npcm7xx_gpio_update_pins(s, diff);
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break;
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case NPCM7XX_GPIO_DOS:
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s->regs[NPCM7XX_GPIO_DOUT] |= value;
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npcm7xx_gpio_update_pins(s, value);
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break;
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case NPCM7XX_GPIO_DOC:
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s->regs[NPCM7XX_GPIO_DOUT] &= ~value;
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npcm7xx_gpio_update_pins(s, value);
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break;
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case NPCM7XX_GPIO_OES:
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s->regs[NPCM7XX_GPIO_OE] |= value;
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npcm7xx_gpio_update_pins(s, value);
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break;
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case NPCM7XX_GPIO_OEC:
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s->regs[NPCM7XX_GPIO_OE] &= ~value;
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npcm7xx_gpio_update_pins(s, value);
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break;
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case NPCM7XX_GPIO_EVTYP:
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case NPCM7XX_GPIO_EVBE:
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case NPCM7XX_GPIO_EVEN:
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s->regs[reg] = value;
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npcm7xx_gpio_update_events(s, 0);
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break;
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case NPCM7XX_GPIO_EVENS:
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s->regs[NPCM7XX_GPIO_EVEN] |= value;
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npcm7xx_gpio_update_events(s, 0);
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break;
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case NPCM7XX_GPIO_EVENC:
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s->regs[NPCM7XX_GPIO_EVEN] &= ~value;
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npcm7xx_gpio_update_events(s, 0);
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break;
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case NPCM7XX_GPIO_EVST:
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s->regs[reg] &= ~value;
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npcm7xx_gpio_update_events(s, 0);
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break;
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case NPCM7XX_GPIO_MP:
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case NPCM7XX_GPIO_DBNC:
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case NPCM7XX_GPIO_OSRC:
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case NPCM7XX_GPIO_ODSC:
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/* Nothing to do; just store the value. */
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s->regs[reg] = value;
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break;
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case NPCM7XX_GPIO_OBL0:
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case NPCM7XX_GPIO_OBL1:
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case NPCM7XX_GPIO_OBL2:
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case NPCM7XX_GPIO_OBL3:
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s->regs[reg] = value;
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qemu_log_mask(LOG_UNIMP, "%s: Blinking is not implemented\n",
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__func__);
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break;
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case NPCM7XX_GPIO_SPLCK:
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case NPCM7XX_GPIO_MPLCK:
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qemu_log_mask(LOG_UNIMP, "%s: Per-pin lock is not implemented\n",
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__func__);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
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DEVICE(s)->canonical_path, addr);
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break;
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}
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}
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static const MemoryRegionOps npcm7xx_gpio_regs_ops = {
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.read = npcm7xx_gpio_regs_read,
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.write = npcm7xx_gpio_regs_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void npcm7xx_gpio_set_input(void *opaque, int line, int level)
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{
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NPCM7xxGPIOState *s = opaque;
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trace_npcm7xx_gpio_set_input(DEVICE(s)->canonical_path, line, level);
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g_assert(line >= 0 && line < NPCM7XX_GPIO_NR_PINS);
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s->ext_driven = deposit32(s->ext_driven, line, 1, level >= 0);
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s->ext_level = deposit32(s->ext_level, line, 1, level > 0);
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npcm7xx_gpio_update_pins(s, BIT(line));
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}
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static void npcm7xx_gpio_enter_reset(Object *obj, ResetType type)
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{
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NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
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memset(s->regs, 0, sizeof(s->regs));
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s->regs[NPCM7XX_GPIO_PU] = s->reset_pu;
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s->regs[NPCM7XX_GPIO_PD] = s->reset_pd;
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s->regs[NPCM7XX_GPIO_OSRC] = s->reset_osrc;
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s->regs[NPCM7XX_GPIO_ODSC] = s->reset_odsc;
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}
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static void npcm7xx_gpio_hold_reset(Object *obj, ResetType type)
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{
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NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
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npcm7xx_gpio_update_pins(s, -1);
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}
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static void npcm7xx_gpio_init(Object *obj)
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{
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NPCM7xxGPIOState *s = NPCM7XX_GPIO(obj);
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DeviceState *dev = DEVICE(obj);
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memory_region_init_io(&s->mmio, obj, &npcm7xx_gpio_regs_ops, s,
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"regs", NPCM7XX_GPIO_REGS_SIZE);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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qdev_init_gpio_in(dev, npcm7xx_gpio_set_input, NPCM7XX_GPIO_NR_PINS);
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qdev_init_gpio_out(dev, s->output, NPCM7XX_GPIO_NR_PINS);
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}
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static const VMStateDescription vmstate_npcm7xx_gpio = {
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.name = "npcm7xx-gpio",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32(pin_level, NPCM7xxGPIOState),
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VMSTATE_UINT32(ext_level, NPCM7xxGPIOState),
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VMSTATE_UINT32(ext_driven, NPCM7xxGPIOState),
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VMSTATE_UINT32_ARRAY(regs, NPCM7xxGPIOState, NPCM7XX_GPIO_NR_REGS),
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VMSTATE_END_OF_LIST(),
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},
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};
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static const Property npcm7xx_gpio_properties[] = {
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/* Bit n set => pin n has pullup enabled by default. */
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DEFINE_PROP_UINT32("reset-pullup", NPCM7xxGPIOState, reset_pu, 0),
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/* Bit n set => pin n has pulldown enabled by default. */
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DEFINE_PROP_UINT32("reset-pulldown", NPCM7xxGPIOState, reset_pd, 0),
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/* Bit n set => pin n has high slew rate by default. */
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DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0),
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/* Bit n set => pin n has high drive strength by default. */
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DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data)
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{
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ResettableClass *reset = RESETTABLE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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QEMU_BUILD_BUG_ON(NPCM7XX_GPIO_REGS_END > NPCM7XX_GPIO_NR_REGS);
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dc->desc = "NPCM7xx GPIO Controller";
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dc->vmsd = &vmstate_npcm7xx_gpio;
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reset->phases.enter = npcm7xx_gpio_enter_reset;
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reset->phases.hold = npcm7xx_gpio_hold_reset;
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device_class_set_props(dc, npcm7xx_gpio_properties);
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}
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static const TypeInfo npcm7xx_gpio_types[] = {
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{
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.name = TYPE_NPCM7XX_GPIO,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NPCM7xxGPIOState),
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.class_init = npcm7xx_gpio_class_init,
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.instance_init = npcm7xx_gpio_init,
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},
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};
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DEFINE_TYPES(npcm7xx_gpio_types);
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