ed1e71dac9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
728 lines
20 KiB
C
728 lines
20 KiB
C
/*
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* QEMU Apple Sound Chip emulation
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*
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* Apple Sound Chip (ASC) 344S0063
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* Enhanced Apple Sound Chip (EASC) 343S1063
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*
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* Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
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* Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/timer.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "audio/audio.h"
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#include "hw/audio/asc.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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/*
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* Linux doesn't provide information about ASC, see arch/m68k/mac/macboing.c
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* and arch/m68k/include/asm/mac_asc.h
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*
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* best information is coming from MAME:
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* https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.h
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* https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.cpp
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* Emulation by R. Belmont
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* or MESS:
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* http://mess.redump.net/mess/driver_info/easc
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*
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* 0x800: VERSION
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* 0x801: MODE
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* 1=FIFO mode,
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* 2=wavetable mode
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* 0x802: CONTROL
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* bit 0=analog or PWM output,
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* 1=stereo/mono,
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* 7=processing time exceeded
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* 0x803: FIFO MODE
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* bit 7=clear FIFO,
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* bit 1="non-ROM companding",
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* bit 0="ROM companding")
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* 0x804: FIFO IRQ STATUS
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* bit 0=ch A 1/2 full,
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* 1=ch A full,
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* 2=ch B 1/2 full,
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* 3=ch B full)
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* 0x805: WAVETABLE CONTROL
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* bits 0-3 wavetables 0-3 start
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* 0x806: VOLUME
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* bits 2-4 = 3 bit internal ASC volume,
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* bits 5-7 = volume control sent to Sony sound chip
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* 0x807: CLOCK RATE
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* 0 = Mac 22257 Hz,
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* 1 = undefined,
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* 2 = 22050 Hz,
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* 3 = 44100 Hz
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* 0x80a: PLAY REC A
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* 0x80f: TEST
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* bits 6-7 = digital test,
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* bits 4-5 = analog test
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* 0x810: WAVETABLE 0 PHASE
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* big-endian 9.15 fixed-point, only 24 bits valid
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* 0x814: WAVETABLE 0 INCREMENT
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* big-endian 9.15 fixed-point, only 24 bits valid
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* 0x818: WAVETABLE 1 PHASE
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* 0x81C: WAVETABLE 1 INCREMENT
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* 0x820: WAVETABLE 2 PHASE
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* 0x824: WAVETABLE 2 INCREMENT
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* 0x828: WAVETABLE 3 PHASE
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* 0x82C: WAVETABLE 3 INCREMENT
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* 0x830: UNKNOWN START
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* NetBSD writes Wavetable data here (are there more
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* wavetables/channels than we know about?)
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* 0x857: UNKNOWN END
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*/
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#define ASC_SIZE 0x2000
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enum {
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ASC_VERSION = 0x00,
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ASC_MODE = 0x01,
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ASC_CONTROL = 0x02,
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ASC_FIFOMODE = 0x03,
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ASC_FIFOIRQ = 0x04,
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ASC_WAVECTRL = 0x05,
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ASC_VOLUME = 0x06,
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ASC_CLOCK = 0x07,
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ASC_PLAYRECA = 0x0a,
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ASC_TEST = 0x0f,
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ASC_WAVETABLE = 0x10
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};
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#define ASC_FIFO_STATUS_HALF_FULL 1
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#define ASC_FIFO_STATUS_FULL_EMPTY 2
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#define ASC_EXTREGS_FIFOCTRL 0x8
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#define ASC_EXTREGS_INTCTRL 0x9
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#define ASC_EXTREGS_CDXA_DECOMP_FILT 0x10
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#define ASC_FIFO_CYCLE_TIME ((NANOSECONDS_PER_SECOND / ASC_FREQ) * \
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0x400)
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static void asc_raise_irq(ASCState *s)
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{
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qemu_set_irq(s->irq, 1);
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}
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static void asc_lower_irq(ASCState *s)
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{
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qemu_set_irq(s->irq, 0);
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}
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static uint8_t asc_fifo_get(ASCFIFOState *fs)
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{
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ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
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bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
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uint8_t val;
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assert(fs->cnt);
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val = fs->fifo[fs->rptr];
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trace_asc_fifo_get('A' + fs->index, fs->rptr, fs->cnt, val);
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fs->rptr++;
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fs->rptr &= 0x3ff;
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fs->cnt--;
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if (fs->cnt <= 0x1ff) {
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/* FIFO less than half full */
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fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
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} else {
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/* FIFO more than half full */
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fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
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}
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if (fs->cnt == 0x1ff && fifo_half_irq_enabled) {
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/* Raise FIFO half full IRQ */
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asc_raise_irq(s);
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}
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if (fs->cnt == 0) {
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/* Raise FIFO empty IRQ */
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fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
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asc_raise_irq(s);
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}
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return val;
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}
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static int generate_fifo(ASCState *s, int maxsamples)
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{
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint8_t *buf = s->mixbuf;
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int i, wcount = 0;
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while (wcount < maxsamples) {
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uint8_t val;
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int16_t d, f0, f1;
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int32_t t;
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int shift, filter;
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bool hasdata = false;
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for (i = 0; i < 2; i++) {
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ASCFIFOState *fs = &s->fifos[i];
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switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) {
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case 0x82:
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/*
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* CD-XA BRR mode: decompress 15 bytes into 28 16-bit
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* samples
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*/
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if (!fs->cnt) {
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val = 0x80;
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break;
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}
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if (fs->xa_cnt == -1) {
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/* Start of packet, get flags */
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fs->xa_flags = asc_fifo_get(fs);
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fs->xa_cnt = 0;
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}
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shift = fs->xa_flags & 0xf;
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filter = fs->xa_flags >> 4;
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f0 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
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(filter << 1) + 1];
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f1 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT +
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(filter << 1)];
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if ((fs->xa_cnt & 1) == 0) {
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if (!fs->cnt) {
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val = 0x80;
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break;
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}
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fs->xa_val = asc_fifo_get(fs);
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d = (fs->xa_val & 0xf) << 12;
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} else {
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d = (fs->xa_val & 0xf0) << 8;
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}
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t = (d >> shift) + (((fs->xa_last[0] * f0) +
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(fs->xa_last[1] * f1) + 32) >> 6);
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if (t < -32768) {
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t = -32768;
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} else if (t > 32767) {
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t = 32767;
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}
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/*
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* CD-XA BRR generates 16-bit signed output, so convert to
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* 8-bit before writing to buffer. Does real hardware do the
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* same?
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*/
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val = (uint8_t)(t / 256) ^ 0x80;
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hasdata = true;
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fs->xa_cnt++;
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fs->xa_last[1] = fs->xa_last[0];
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fs->xa_last[0] = (int16_t)t;
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if (fs->xa_cnt == 28) {
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/* End of packet */
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fs->xa_cnt = -1;
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}
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break;
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default:
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/* fallthrough */
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case 0x80:
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/* Raw mode */
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if (fs->cnt) {
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val = asc_fifo_get(fs);
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hasdata = true;
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} else {
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val = 0x80;
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}
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break;
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}
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buf[wcount * 2 + i] = val;
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}
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if (!hasdata) {
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break;
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}
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wcount++;
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}
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/*
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* MacOS (un)helpfully leaves the FIFO engine running even when it has
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* finished writing out samples, but still expects the FIFO empty
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* interrupts to be generated for each FIFO cycle (without these interrupts
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* MacOS will freeze)
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*/
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if (s->fifos[0].cnt == 0 && s->fifos[1].cnt == 0) {
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if (!s->fifo_empty_ns) {
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/* FIFO has completed first empty cycle */
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s->fifo_empty_ns = now;
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} else if (now > (s->fifo_empty_ns + ASC_FIFO_CYCLE_TIME)) {
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/* FIFO has completed entire cycle with no data */
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s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL |
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ASC_FIFO_STATUS_FULL_EMPTY;
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s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL |
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ASC_FIFO_STATUS_FULL_EMPTY;
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s->fifo_empty_ns = now;
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asc_raise_irq(s);
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}
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} else {
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/* FIFO contains data, reset empty time */
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s->fifo_empty_ns = 0;
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}
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return wcount;
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}
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static int generate_wavetable(ASCState *s, int maxsamples)
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{
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uint8_t *buf = s->mixbuf;
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int channel, count = 0;
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while (count < maxsamples) {
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uint32_t left = 0, right = 0;
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uint8_t sample;
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for (channel = 0; channel < 4; channel++) {
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ASCFIFOState *fs = &s->fifos[channel >> 1];
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int chanreg = ASC_WAVETABLE + (channel << 3);
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uint32_t phase, incr, offset;
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phase = ldl_be_p(&s->regs[chanreg]);
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incr = ldl_be_p(&s->regs[chanreg + sizeof(uint32_t)]);
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phase += incr;
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offset = (phase >> 15) & 0x1ff;
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sample = fs->fifo[0x200 * (channel >> 1) + offset];
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stl_be_p(&s->regs[chanreg], phase);
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left += sample;
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right += sample;
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}
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buf[count * 2] = left >> 2;
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buf[count * 2 + 1] = right >> 2;
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count++;
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}
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return count;
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}
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static void asc_out_cb(void *opaque, int free_b)
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{
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ASCState *s = opaque;
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int samples, generated;
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if (free_b == 0) {
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return;
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}
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samples = MIN(s->samples, free_b >> s->shift);
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switch (s->regs[ASC_MODE] & 3) {
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default:
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/* Off */
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generated = 0;
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break;
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case 1:
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/* FIFO mode */
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generated = generate_fifo(s, samples);
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break;
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case 2:
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/* Wave table mode */
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generated = generate_wavetable(s, samples);
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break;
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}
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if (!generated) {
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/* Workaround for audio underflow bug on Windows dsound backend */
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int silent_samples = muldiv64(now - s->fifo_empty_ns,
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NANOSECONDS_PER_SECOND, ASC_FREQ);
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if (silent_samples > ASC_FIFO_CYCLE_TIME / 2) {
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/*
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* No new FIFO data within half a cycle time (~23ms) so fill the
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* entire available buffer with silence. This prevents an issue
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* with the Windows dsound backend whereby the sound appears to
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* loop because the FIFO has run out of data, and the driver
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* reuses the stale content in its circular audio buffer.
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*/
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AUD_write(s->voice, s->silentbuf, samples << s->shift);
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}
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return;
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}
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AUD_write(s->voice, s->mixbuf, generated << s->shift);
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}
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static uint64_t asc_fifo_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ASCFIFOState *fs = opaque;
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trace_asc_read_fifo('A' + fs->index, addr, size, fs->fifo[addr]);
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return fs->fifo[addr];
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}
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static void asc_fifo_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ASCFIFOState *fs = opaque;
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ASCState *s = container_of(fs, ASCState, fifos[fs->index]);
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bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1;
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trace_asc_write_fifo('A' + fs->index, addr, size, fs->wptr, fs->cnt, value);
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if (s->regs[ASC_MODE] == 1) {
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fs->fifo[fs->wptr++] = value;
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fs->wptr &= 0x3ff;
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fs->cnt++;
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if (fs->cnt <= 0x1ff) {
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/* FIFO less than half full */
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fs->int_status |= ASC_FIFO_STATUS_HALF_FULL;
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} else {
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/* FIFO at least half full */
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fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL;
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}
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if (fs->cnt == 0x200 && fifo_half_irq_enabled) {
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/* Raise FIFO half full interrupt */
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asc_raise_irq(s);
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}
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if (fs->cnt == 0x3ff) {
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/* Raise FIFO full interrupt */
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fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY;
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asc_raise_irq(s);
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}
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} else {
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fs->fifo[addr] = value;
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}
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return;
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}
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static const MemoryRegionOps asc_fifo_ops = {
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.read = asc_fifo_read,
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.write = asc_fifo_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void asc_fifo_reset(ASCFIFOState *fs);
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static uint64_t asc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ASCState *s = opaque;
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uint64_t prev, value;
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switch (addr) {
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case ASC_VERSION:
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switch (s->type) {
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default:
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case ASC_TYPE_ASC:
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value = 0;
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break;
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case ASC_TYPE_EASC:
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value = 0xb0;
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break;
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}
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break;
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case ASC_FIFOIRQ:
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prev = (s->fifos[0].int_status & 0x3) |
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(s->fifos[1].int_status & 0x3) << 2;
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s->fifos[0].int_status = 0;
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s->fifos[1].int_status = 0;
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asc_lower_irq(s);
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value = prev;
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break;
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default:
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value = s->regs[addr];
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break;
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}
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trace_asc_read_reg(addr, size, value);
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return value;
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}
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static void asc_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ASCState *s = opaque;
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switch (addr) {
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case ASC_MODE:
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value &= 3;
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if (value != s->regs[ASC_MODE]) {
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asc_fifo_reset(&s->fifos[0]);
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asc_fifo_reset(&s->fifos[1]);
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asc_lower_irq(s);
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if (value != 0) {
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AUD_set_active_out(s->voice, 1);
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} else {
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AUD_set_active_out(s->voice, 0);
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}
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}
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break;
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case ASC_FIFOMODE:
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if (value & 0x80) {
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asc_fifo_reset(&s->fifos[0]);
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asc_fifo_reset(&s->fifos[1]);
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asc_lower_irq(s);
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}
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break;
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case ASC_WAVECTRL:
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break;
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case ASC_VOLUME:
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{
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int vol = (value & 0xe0);
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AUD_set_volume_out(s->voice, 0, vol, vol);
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break;
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}
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}
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trace_asc_write_reg(addr, size, value);
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s->regs[addr] = value;
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}
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static const MemoryRegionOps asc_regs_ops = {
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.read = asc_read,
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.write = asc_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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}
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};
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static uint64_t asc_ext_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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ASCFIFOState *fs = opaque;
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uint64_t value;
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value = fs->extregs[addr];
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trace_asc_read_extreg('A' + fs->index, addr, size, value);
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return value;
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}
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static void asc_ext_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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ASCFIFOState *fs = opaque;
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|
|
trace_asc_write_extreg('A' + fs->index, addr, size, value);
|
|
|
|
fs->extregs[addr] = value;
|
|
}
|
|
|
|
static const MemoryRegionOps asc_extregs_ops = {
|
|
.read = asc_ext_read,
|
|
.write = asc_ext_write,
|
|
.impl = {
|
|
.min_access_size = 1,
|
|
.max_access_size = 1,
|
|
},
|
|
.endianness = DEVICE_BIG_ENDIAN,
|
|
};
|
|
|
|
static int asc_post_load(void *opaque, int version)
|
|
{
|
|
ASCState *s = ASC(opaque);
|
|
|
|
if (s->regs[ASC_MODE] != 0) {
|
|
AUD_set_active_out(s->voice, 1);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_asc_fifo = {
|
|
.name = "apple-sound-chip.fifo",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.fields = (const VMStateField[]) {
|
|
VMSTATE_UINT8_ARRAY(fifo, ASCFIFOState, ASC_FIFO_SIZE),
|
|
VMSTATE_UINT8(int_status, ASCFIFOState),
|
|
VMSTATE_INT32(cnt, ASCFIFOState),
|
|
VMSTATE_INT32(wptr, ASCFIFOState),
|
|
VMSTATE_INT32(rptr, ASCFIFOState),
|
|
VMSTATE_UINT8_ARRAY(extregs, ASCFIFOState, ASC_EXTREG_SIZE),
|
|
VMSTATE_INT32(xa_cnt, ASCFIFOState),
|
|
VMSTATE_UINT8(xa_val, ASCFIFOState),
|
|
VMSTATE_UINT8(xa_flags, ASCFIFOState),
|
|
VMSTATE_INT16_ARRAY(xa_last, ASCFIFOState, 2),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_asc = {
|
|
.name = "apple-sound-chip",
|
|
.version_id = 0,
|
|
.minimum_version_id = 0,
|
|
.post_load = asc_post_load,
|
|
.fields = (const VMStateField[]) {
|
|
VMSTATE_STRUCT_ARRAY(fifos, ASCState, 2, 0, vmstate_asc_fifo,
|
|
ASCFIFOState),
|
|
VMSTATE_UINT8_ARRAY(regs, ASCState, ASC_REG_SIZE),
|
|
VMSTATE_INT64(fifo_empty_ns, ASCState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void asc_fifo_reset(ASCFIFOState *fs)
|
|
{
|
|
fs->wptr = 0;
|
|
fs->rptr = 0;
|
|
fs->cnt = 0;
|
|
fs->xa_cnt = -1;
|
|
fs->int_status = 0;
|
|
}
|
|
|
|
static void asc_fifo_init(ASCFIFOState *fs, int index)
|
|
{
|
|
ASCState *s = container_of(fs, ASCState, fifos[index]);
|
|
char *name;
|
|
|
|
fs->index = index;
|
|
name = g_strdup_printf("asc.fifo%c", 'A' + index);
|
|
memory_region_init_io(&fs->mem_fifo, OBJECT(s), &asc_fifo_ops, fs,
|
|
name, ASC_FIFO_SIZE);
|
|
g_free(name);
|
|
|
|
name = g_strdup_printf("asc.extregs%c", 'A' + index);
|
|
memory_region_init_io(&fs->mem_extregs, OBJECT(s), &asc_extregs_ops,
|
|
fs, name, ASC_EXTREG_SIZE);
|
|
g_free(name);
|
|
}
|
|
|
|
static void asc_reset_hold(Object *obj, ResetType type)
|
|
{
|
|
ASCState *s = ASC(obj);
|
|
|
|
AUD_set_active_out(s->voice, 0);
|
|
|
|
memset(s->regs, 0, sizeof(s->regs));
|
|
asc_fifo_reset(&s->fifos[0]);
|
|
asc_fifo_reset(&s->fifos[1]);
|
|
s->fifo_empty_ns = 0;
|
|
|
|
if (s->type == ASC_TYPE_ASC) {
|
|
/* FIFO half full IRQs enabled by default */
|
|
s->fifos[0].extregs[ASC_EXTREGS_INTCTRL] = 1;
|
|
s->fifos[1].extregs[ASC_EXTREGS_INTCTRL] = 1;
|
|
}
|
|
}
|
|
|
|
static void asc_unrealize(DeviceState *dev)
|
|
{
|
|
ASCState *s = ASC(dev);
|
|
|
|
g_free(s->mixbuf);
|
|
g_free(s->silentbuf);
|
|
|
|
AUD_remove_card(&s->card);
|
|
}
|
|
|
|
static void asc_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
ASCState *s = ASC(dev);
|
|
struct audsettings as;
|
|
|
|
if (!AUD_register_card("Apple Sound Chip", &s->card, errp)) {
|
|
return;
|
|
}
|
|
|
|
as.freq = ASC_FREQ;
|
|
as.nchannels = 2;
|
|
as.fmt = AUDIO_FORMAT_U8;
|
|
as.endianness = AUDIO_HOST_ENDIANNESS;
|
|
|
|
s->voice = AUD_open_out(&s->card, s->voice, "asc.out", s, asc_out_cb,
|
|
&as);
|
|
s->shift = 1;
|
|
s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift;
|
|
s->mixbuf = g_malloc0(s->samples << s->shift);
|
|
|
|
s->silentbuf = g_malloc0(s->samples << s->shift);
|
|
memset(s->silentbuf, 0x80, s->samples << s->shift);
|
|
|
|
/* Add easc registers if required */
|
|
if (s->type == ASC_TYPE_EASC) {
|
|
memory_region_add_subregion(&s->asc, ASC_EXTREG_OFFSET,
|
|
&s->fifos[0].mem_extregs);
|
|
memory_region_add_subregion(&s->asc,
|
|
ASC_EXTREG_OFFSET + ASC_EXTREG_SIZE,
|
|
&s->fifos[1].mem_extregs);
|
|
}
|
|
}
|
|
|
|
static void asc_init(Object *obj)
|
|
{
|
|
ASCState *s = ASC(obj);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
memory_region_init(&s->asc, OBJECT(obj), "asc", ASC_SIZE);
|
|
|
|
asc_fifo_init(&s->fifos[0], 0);
|
|
asc_fifo_init(&s->fifos[1], 1);
|
|
|
|
memory_region_add_subregion(&s->asc, ASC_FIFO_OFFSET,
|
|
&s->fifos[0].mem_fifo);
|
|
memory_region_add_subregion(&s->asc,
|
|
ASC_FIFO_OFFSET + ASC_FIFO_SIZE,
|
|
&s->fifos[1].mem_fifo);
|
|
|
|
memory_region_init_io(&s->mem_regs, OBJECT(obj), &asc_regs_ops, s,
|
|
"asc.regs", ASC_REG_SIZE);
|
|
memory_region_add_subregion(&s->asc, ASC_REG_OFFSET, &s->mem_regs);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
|
sysbus_init_mmio(sbd, &s->asc);
|
|
}
|
|
|
|
static const Property asc_properties[] = {
|
|
DEFINE_AUDIO_PROPERTIES(ASCState, card),
|
|
DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void asc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
ResettableClass *rc = RESETTABLE_CLASS(oc);
|
|
|
|
dc->realize = asc_realize;
|
|
dc->unrealize = asc_unrealize;
|
|
set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
|
|
dc->vmsd = &vmstate_asc;
|
|
device_class_set_props(dc, asc_properties);
|
|
rc->phases.hold = asc_reset_hold;
|
|
}
|
|
|
|
static const TypeInfo asc_info_types[] = {
|
|
{
|
|
.name = TYPE_ASC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(ASCState),
|
|
.instance_init = asc_init,
|
|
.class_init = asc_class_init,
|
|
},
|
|
};
|
|
|
|
DEFINE_TYPES(asc_info_types)
|