0bb446d8b0
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
499 lines
18 KiB
C
499 lines
18 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu.h"
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#include "elf.h"
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#include "cpu_loop-common.h"
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#include "hw/semihosting/common-semi.h"
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#define get_user_code_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_code_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define get_user_data_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_data_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define put_user_data_u32(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap32(__x); \
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} \
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put_user_u32(__x, (gaddr)); \
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})
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#define put_user_data_u16(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap16(__x); \
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} \
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put_user_u16(__x, (gaddr)); \
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})
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/* Commpage handling -- there is no commpage for AArch64 */
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/*
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* See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
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* Input:
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* r0 = pointer to oldval
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* r1 = pointer to newval
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* r2 = pointer to target value
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*
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* Output:
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* r0 = 0 if *ptr was changed, non-0 if no exchange happened
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* C set if *ptr was changed, clear if no exchange happened
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*
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* Note segv's in kernel helpers are a bit tricky, we can set the
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* data address sensibly but the PC address is just the entry point.
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*/
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static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
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{
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uint64_t oldval, newval, val;
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uint32_t addr, cpsr;
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target_siginfo_t info;
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/* Based on the 32 bit code in do_kernel_trap */
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/* XXX: This only works between threads, not between processes.
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It's probably possible to implement this with native host
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operations. However things like ldrex/strex are much harder so
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there's not much point trying. */
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start_exclusive();
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cpsr = cpsr_read(env);
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addr = env->regs[2];
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if (get_user_u64(oldval, env->regs[0])) {
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env->exception.vaddress = env->regs[0];
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goto segv;
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};
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if (get_user_u64(newval, env->regs[1])) {
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env->exception.vaddress = env->regs[1];
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goto segv;
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};
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if (get_user_u64(val, addr)) {
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env->exception.vaddress = addr;
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goto segv;
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}
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if (val == oldval) {
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val = newval;
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if (put_user_u64(val, addr)) {
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env->exception.vaddress = addr;
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goto segv;
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};
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env->regs[0] = 0;
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cpsr |= CPSR_C;
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} else {
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env->regs[0] = -1;
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cpsr &= ~CPSR_C;
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}
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cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
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end_exclusive();
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return;
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segv:
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end_exclusive();
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/* We get the PC of the entry address - which is as good as anything,
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on a real kernel what you get depends on which mode it uses. */
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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/* XXX: check env->error_code */
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = env->exception.vaddress;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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/* Handle a jump to the kernel code page. */
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static int
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do_kernel_trap(CPUARMState *env)
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{
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uint32_t addr;
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uint32_t cpsr;
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uint32_t val;
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switch (env->regs[15]) {
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case 0xffff0fa0: /* __kernel_memory_barrier */
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/* ??? No-op. Will need to do better for SMP. */
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break;
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case 0xffff0fc0: /* __kernel_cmpxchg */
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/* XXX: This only works between threads, not between processes.
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It's probably possible to implement this with native host
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operations. However things like ldrex/strex are much harder so
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there's not much point trying. */
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start_exclusive();
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cpsr = cpsr_read(env);
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addr = env->regs[2];
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/* FIXME: This should SEGV if the access fails. */
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if (get_user_u32(val, addr))
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val = ~env->regs[0];
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if (val == env->regs[0]) {
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val = env->regs[1];
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/* FIXME: Check for segfaults. */
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put_user_u32(val, addr);
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env->regs[0] = 0;
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cpsr |= CPSR_C;
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} else {
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env->regs[0] = -1;
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cpsr &= ~CPSR_C;
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}
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cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
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end_exclusive();
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break;
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case 0xffff0fe0: /* __kernel_get_tls */
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env->regs[0] = cpu_get_tls(env);
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break;
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case 0xffff0f60: /* __kernel_cmpxchg64 */
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arm_kernel_cmpxchg64_helper(env);
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break;
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default:
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return 1;
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}
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/* Jump back to the caller. */
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addr = env->regs[14];
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if (addr & 1) {
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env->thumb = 1;
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addr &= ~1;
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}
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env->regs[15] = addr;
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return 0;
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}
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static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb)
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{
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/*
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* Return true if this insn is one of the three magic UDF insns
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* which the kernel treats as breakpoint insns.
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*/
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if (!is_thumb) {
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return (opcode & 0x0fffffff) == 0x07f001f0;
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} else {
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/*
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* Note that we get the two halves of the 32-bit T32 insn
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* in the opposite order to the value the kernel uses in
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* its undef_hook struct.
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*/
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return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0);
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}
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}
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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unsigned int n, insn;
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target_siginfo_t info;
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uint32_t addr;
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abi_ulong ret;
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for(;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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case EXCP_UDEF:
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case EXCP_NOCP:
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case EXCP_INVSTATE:
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{
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TaskState *ts = cs->opaque;
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uint32_t opcode;
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int rc;
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/* we handle the FPU emulation here, as Linux */
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/* we get the opcode */
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/* FIXME - what to do if get_user() fails? */
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get_user_code_u32(opcode, env->regs[15], env);
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/*
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* The Linux kernel treats some UDF patterns specially
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* to use as breakpoints (instead of the architectural
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* bkpt insn). These should trigger a SIGTRAP rather
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* than SIGILL.
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*/
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if (insn_is_linux_bkpt(opcode, env->thumb)) {
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goto excp_debug;
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}
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rc = EmulateAll(opcode, &ts->fpa, env);
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if (rc == 0) { /* illegal instruction */
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLOPN;
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info._sifields._sigfault._addr = env->regs[15];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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} else if (rc < 0) { /* FP exception */
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int arm_fpe=0;
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/* translate softfloat flags to FPSR flags */
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if (-rc & float_flag_invalid)
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arm_fpe |= BIT_IOC;
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if (-rc & float_flag_divbyzero)
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arm_fpe |= BIT_DZC;
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if (-rc & float_flag_overflow)
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arm_fpe |= BIT_OFC;
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if (-rc & float_flag_underflow)
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arm_fpe |= BIT_UFC;
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if (-rc & float_flag_inexact)
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arm_fpe |= BIT_IXC;
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FPSR fpsr = ts->fpa.fpsr;
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//printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
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if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
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info.si_signo = TARGET_SIGFPE;
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info.si_errno = 0;
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/* ordered by priority, least first */
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if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
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if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
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if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
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if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
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if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
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info._sifields._sigfault._addr = env->regs[15];
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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} else {
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env->regs[15] += 4;
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}
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/* accumulate unenabled exceptions */
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if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
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fpsr |= BIT_IXC;
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if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
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fpsr |= BIT_UFC;
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if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
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fpsr |= BIT_OFC;
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if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
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fpsr |= BIT_DZC;
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if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
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fpsr |= BIT_IOC;
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ts->fpa.fpsr=fpsr;
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} else { /* everything OK */
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/* increment PC */
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env->regs[15] += 4;
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}
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}
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break;
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case EXCP_SWI:
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{
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env->eabi = 1;
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/* system call */
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if (env->thumb) {
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/* Thumb is always EABI style with syscall number in r7 */
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n = env->regs[7];
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} else {
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/*
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* Equivalent of kernel CONFIG_OABI_COMPAT: read the
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* Arm SVC insn to extract the immediate, which is the
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* syscall number in OABI.
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*/
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/* FIXME - what to do if get_user() fails? */
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get_user_code_u32(insn, env->regs[15] - 4, env);
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n = insn & 0xffffff;
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if (n == 0) {
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/* zero immediate: EABI, syscall number in r7 */
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n = env->regs[7];
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} else {
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/*
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* This XOR matches the kernel code: an immediate
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* in the valid range (0x900000 .. 0x9fffff) is
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* converted into the correct EABI-style syscall
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* number; invalid immediates end up as values
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* > 0xfffff and are handled below as out-of-range.
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*/
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n ^= ARM_SYSCALL_BASE;
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env->eabi = 0;
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}
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}
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if (n > ARM_NR_BASE) {
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switch (n) {
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case ARM_NR_cacheflush:
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/* nop */
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break;
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case ARM_NR_set_tls:
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cpu_set_tls(env, env->regs[0]);
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env->regs[0] = 0;
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break;
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case ARM_NR_breakpoint:
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env->regs[15] -= env->thumb ? 2 : 4;
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goto excp_debug;
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case ARM_NR_get_tls:
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env->regs[0] = cpu_get_tls(env);
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break;
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default:
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if (n < 0xf0800) {
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/*
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* Syscalls 0xf0000..0xf07ff (or 0x9f0000..
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* 0x9f07ff in OABI numbering) are defined
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* to return -ENOSYS rather than raising
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* SIGILL. Note that we have already
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* removed the 0x900000 prefix.
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*/
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qemu_log_mask(LOG_UNIMP,
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"qemu: Unsupported ARM syscall: 0x%x\n",
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n);
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env->regs[0] = -TARGET_ENOSYS;
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} else {
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/*
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* Otherwise SIGILL. This includes any SWI with
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* immediate not originally 0x9fxxxx, because
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* of the earlier XOR.
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*/
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_ILLTRP;
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info._sifields._sigfault._addr = env->regs[15];
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if (env->thumb) {
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info._sifields._sigfault._addr -= 2;
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} else {
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info._sifields._sigfault._addr -= 4;
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}
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queue_signal(env, info.si_signo,
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QEMU_SI_FAULT, &info);
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}
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break;
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}
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} else {
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ret = do_syscall(env,
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n,
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env->regs[0],
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env->regs[1],
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env->regs[2],
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env->regs[3],
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env->regs[4],
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env->regs[5],
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0, 0);
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if (ret == -TARGET_ERESTARTSYS) {
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env->regs[15] -= env->thumb ? 2 : 4;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->regs[0] = ret;
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}
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}
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}
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break;
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case EXCP_SEMIHOST:
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env->regs[0] = do_common_semihosting(cs);
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env->regs[15] += env->thumb ? 2 : 4;
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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addr = env->exception.vaddress;
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{
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info.si_signo = TARGET_SIGSEGV;
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info.si_errno = 0;
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/* XXX: check env->error_code */
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info.si_code = TARGET_SEGV_MAPERR;
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info._sifields._sigfault._addr = addr;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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break;
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case EXCP_DEBUG:
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case EXCP_BKPT:
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excp_debug:
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info.si_signo = TARGET_SIGTRAP;
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info.si_errno = 0;
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info.si_code = TARGET_TRAP_BRKPT;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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break;
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case EXCP_KERNEL_TRAP:
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if (do_kernel_trap(env))
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goto error;
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break;
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case EXCP_YIELD:
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/* nothing to do here for user-mode, just resume guest code */
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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error:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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TaskState *ts = cpu->opaque;
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struct image_info *info = ts->info;
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int i;
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cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
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CPSRWriteByInstr);
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for(i = 0; i < 16; i++) {
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env->regs[i] = regs->uregs[i];
|
|
}
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
/* Enable BE8. */
|
|
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
|
|
&& (info->elf_flags & EF_ARM_BE8)) {
|
|
env->uncached_cpsr |= CPSR_E;
|
|
env->cp15.sctlr_el[1] |= SCTLR_E0E;
|
|
} else {
|
|
env->cp15.sctlr_el[1] |= SCTLR_B;
|
|
}
|
|
arm_rebuild_hflags(env);
|
|
#endif
|
|
|
|
ts->stack_base = info->start_stack;
|
|
ts->heap_base = info->brk;
|
|
/* This will be filled in on the first SYS_HEAPINFO call. */
|
|
ts->heap_limit = 0;
|
|
}
|