3635502dd0
Introduce a new opcode for negative setcond. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
174 lines
6.3 KiB
C
174 lines
6.3 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* This code implements a TCG which does not generate machine code for some
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* real target machine but which generates virtual machine code for an
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* interpreter. Interpreted pseudo code is slow, but it works on any host.
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*
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* Some remarks might help in understanding the code:
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*
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* "target" or "TCG target" is the machine which runs the generated code.
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* This is different to the usual meaning in QEMU where "target" is the
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* emulated machine. So normally QEMU host is identical to TCG target.
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* Here the TCG target is a virtual machine, but this virtual machine must
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* use the same word size like the real machine.
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* Therefore, we need both 32 and 64 bit virtual machines (interpreter).
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*/
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#ifndef TCG_TARGET_H
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#define TCG_TARGET_H
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#define TCG_TARGET_INTERPRETER 1
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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/* Optional instructions. */
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_eqv_i32 1
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#define TCG_TARGET_HAS_nand_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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#define TCG_TARGET_HAS_ctpop_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_orc_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_extr_i64_i32 0
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_andc_i64 1
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#define TCG_TARGET_HAS_eqv_i64 1
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#define TCG_TARGET_HAS_nand_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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#define TCG_TARGET_HAS_ctpop_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_orc_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#define TCG_TARGET_HAS_muls2_i64 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_muluh_i64 0
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#define TCG_TARGET_HAS_mulsh_i64 0
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#else
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#define TCG_TARGET_HAS_mulu2_i32 1
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#endif /* TCG_TARGET_REG_BITS == 64 */
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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/* Number of registers available. */
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#define TCG_TARGET_NB_REGS 16
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/* List of registers which are used by TCG. */
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typedef enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_TMP = TCG_REG_R13,
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TCG_AREG0 = TCG_REG_R14,
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TCG_REG_CALL_STACK = TCG_REG_R15,
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} TCGReg;
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/* Used for function call generation. */
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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#define TCG_TARGET_STACK_ALIGN 8
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#if TCG_TARGET_REG_BITS == 32
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# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN
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# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
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#else
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# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
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# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
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# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL
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#endif
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#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
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#define HAVE_TCG_QEMU_TB_EXEC
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#define TCG_TARGET_NEED_POOL_LABELS
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/* We could notice __i386__ or __s390x__ and reduce the barriers depending
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on the host. But if you want performance, you use the normal backend.
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We prefer consistency across hosts on this. */
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#define TCG_TARGET_DEFAULT_MO (0)
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#endif /* TCG_TARGET_H */
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