33417e7025
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@354 c046a42c-6fe2-441c-8c8c-71466251a162
387 lines
11 KiB
C
387 lines
11 KiB
C
/*
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* internal execution defines for qemu
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* allow to see translation results - the slowdown should be negligible, so we leave it */
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#define DEBUG_DISAS
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#ifndef glue
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define stringify(s) tostring(s)
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#define tostring(s) #s
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#endif
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#if GCC_MAJOR < 3
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#define __builtin_expect(x, n) (x)
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#endif
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/* is_jmp field values */
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#define DISAS_NEXT 0 /* next instruction can be analyzed */
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#define DISAS_JUMP 1 /* only pc was modified dynamically */
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#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
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#define DISAS_TB_JUMP 3 /* only pc was modified statically */
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struct TranslationBlock;
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 32
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#define OPC_BUF_SIZE 512
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
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extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
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extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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#if defined(TARGET_I386)
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#define GEN_FLAG_CODE32_SHIFT 0
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#define GEN_FLAG_ADDSEG_SHIFT 1
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#define GEN_FLAG_SS32_SHIFT 2
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#define GEN_FLAG_VM_SHIFT 3
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#define GEN_FLAG_ST_SHIFT 4
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#define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */
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#define GEN_FLAG_CPL_SHIFT 9
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#define GEN_FLAG_SOFT_MMU_SHIFT 11
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#define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */
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void optimize_flags_init(void);
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#endif
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extern FILE *logfile;
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extern int loglevel;
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int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
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int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
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void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
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int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
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int max_code_size, int *gen_code_size_ptr);
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int cpu_restore_state(struct TranslationBlock *tb,
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CPUState *env, unsigned long searched_pc);
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void cpu_exec_init(void);
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int page_unprotect(unsigned long address);
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void page_unmap(void);
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void tlb_flush_page(CPUState *env, uint32_t addr);
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void tlb_flush(CPUState *env);
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#define CODE_GEN_MAX_SIZE 65536
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_HASH_BITS 15
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#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
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/* maximum total translate dcode allocated */
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#define CODE_GEN_BUFFER_SIZE (2048 * 1024)
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//#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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#if defined(__powerpc__)
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#define USE_DIRECT_JUMP
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#endif
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typedef struct TranslationBlock {
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unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
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unsigned long cs_base; /* CS base for this block */
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unsigned int flags; /* flags defining in which context the code was generated */
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uint16_t size; /* size of target code for this block (1 <=
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size <= TARGET_PAGE_SIZE) */
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uint8_t *tc_ptr; /* pointer to the translated code */
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struct TranslationBlock *hash_next; /* next matching block */
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struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
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/* the following data are used to directly call another TB from
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the code of this one. */
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uint16_t tb_next_offset[2]; /* offset of original jump target */
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#ifdef USE_DIRECT_JUMP
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uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
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#else
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uint32_t tb_next[2]; /* address of jump generated code */
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#endif
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/* list of TBs jumping to this one. This is a circular list using
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the two least significant bits of the pointers to tell what is
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the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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jmp_first */
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struct TranslationBlock *jmp_next[2];
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struct TranslationBlock *jmp_first;
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} TranslationBlock;
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static inline unsigned int tb_hash_func(unsigned long pc)
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{
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return pc & (CODE_GEN_HASH_SIZE - 1);
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}
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TranslationBlock *tb_alloc(unsigned long pc);
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void tb_flush(void);
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void tb_link(TranslationBlock *tb);
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extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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extern uint8_t *code_gen_ptr;
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/* find a translation block in the translation cache. If not found,
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return NULL and the pointer to the last element of the list in pptb */
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static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
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unsigned long pc,
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unsigned long cs_base,
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unsigned int flags)
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{
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TranslationBlock **ptb, *tb;
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unsigned int h;
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h = tb_hash_func(pc);
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ptb = &tb_hash[h];
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for(;;) {
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tb = *ptb;
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if (!tb)
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break;
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if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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return tb;
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ptb = &tb->hash_next;
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}
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*pptb = ptb;
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return NULL;
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}
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#if defined(__powerpc__)
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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uint32_t val, *ptr;
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unsigned long offset;
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offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);
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/* patch the branch destination */
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ptr = (uint32_t *)offset;
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val = *ptr;
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val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc);
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*ptr = val;
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/* flush icache */
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asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
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asm volatile ("sync" : : : "memory");
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asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#else
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/* set the jump target */
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static inline void tb_set_jmp_target(TranslationBlock *tb,
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int n, unsigned long addr)
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{
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tb->tb_next[n] = addr;
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}
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#endif
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static inline void tb_add_jump(TranslationBlock *tb, int n,
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TranslationBlock *tb_next)
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{
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/* NOTE: this test is only needed for thread safety */
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if (!tb->jmp_next[n]) {
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/* patch the native jump address */
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tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
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/* add in TB jmp circular list */
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tb->jmp_next[n] = tb_next->jmp_first;
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tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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}
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}
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TranslationBlock *tb_find_pc(unsigned long pc_ptr);
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#ifndef offsetof
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#define offsetof(type, field) ((size_t) &((type *)0)->field)
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#endif
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#if defined(__powerpc__)
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/* on PowerPC we patch the jump instruction directly */
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#define JUMP_TB(tbparam, n, eip)\
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do {\
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static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
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asm volatile ("b %0" : : "i" (&__op_jmp ## n));\
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label ## n:\
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T0 = (long)(tbparam) + (n);\
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EIP = eip;\
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} while (0)
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#else
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/* jump to next block operations (more portable code, does not need
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cache flushing, but slower because of indirect jump) */
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#define JUMP_TB(tbparam, n, eip)\
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do {\
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static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
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static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
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goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
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label ## n:\
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T0 = (long)(tbparam) + (n);\
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EIP = eip;\
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dummy_label ## n:\
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EXIT_TB();\
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} while (0)
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#endif
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/* physical memory access */
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#define IO_MEM_NB_ENTRIES 256
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#define TLB_INVALID_MASK (1 << 3)
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#define IO_MEM_SHIFT 4
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#define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT)
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unsigned long physpage_find(unsigned long page);
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extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
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extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
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#ifdef __powerpc__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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"0: lwarx %0,0,%1 ;"
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" xor. %0,%3,%0;"
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" bne 1f;"
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" stwcx. %2,0,%1;"
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" bne- 0b;"
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"1: "
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: "=&r" (ret)
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: "r" (p), "r" (1), "r" (0)
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: "cr0", "memory");
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return ret;
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}
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#endif
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#ifdef __i386__
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static inline int testandset (int *p)
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{
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char ret;
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long int readval;
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__asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
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: "=q" (ret), "=m" (*p), "=a" (readval)
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: "r" (1), "m" (*p), "a" (0)
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: "memory");
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return ret;
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}
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#endif
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#ifdef __s390__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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" jl 0b"
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: "=&d" (ret)
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: "r" (1), "a" (p), "0" (*p)
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: "cc", "memory" );
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return ret;
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}
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#endif
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#ifdef __alpha__
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static inline int testandset (int *p)
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{
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int ret;
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unsigned long one;
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__asm__ __volatile__ ("0: mov 1,%2\n"
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" ldl_l %0,%1\n"
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" stl_c %2,%1\n"
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" beq %2,1f\n"
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".subsection 2\n"
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"1: br 0b\n"
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".previous"
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: "=r" (ret), "=m" (*p), "=r" (one)
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: "m" (*p));
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return ret;
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}
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#endif
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#ifdef __sparc__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (ret)
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: "r" (p)
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: "memory");
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return (ret ? 1 : 0);
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}
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#endif
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#ifdef __arm__
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static inline int testandset (int *spinlock)
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{
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register unsigned int ret;
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__asm__ __volatile__("swp %0, %1, [%2]"
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: "=r"(ret)
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: "0"(1), "r"(spinlock));
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return ret;
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}
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#endif
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typedef int spinlock_t;
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#define SPIN_LOCK_UNLOCKED 0
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#if 1
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static inline void spin_lock(spinlock_t *lock)
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{
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while (testandset(lock));
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}
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static inline void spin_unlock(spinlock_t *lock)
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{
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*lock = 0;
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}
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static inline int spin_trylock(spinlock_t *lock)
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{
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return !testandset(lock);
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}
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#else
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static inline void spin_lock(spinlock_t *lock)
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{
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}
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static inline void spin_unlock(spinlock_t *lock)
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{
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}
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static inline int spin_trylock(spinlock_t *lock)
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{
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return 1;
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}
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#endif
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extern spinlock_t tb_lock;
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