 e3d0814368
			
		
	
	
		e3d0814368
		
	
	
	
	
		
			
			Use device_class_set_legacy_reset() instead of opencoding an
assignment to DeviceClass::reset. This change was produced
with:
 spatch --macro-file scripts/cocci-macro-file.h \
    --sp-file scripts/coccinelle/device-reset.cocci \
    --keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
		
	
			
		
			
				
	
	
		
			283 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			283 lines
		
	
	
		
			8.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Broadcom Serial Controller (BSC)
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|  *
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|  * Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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|  *
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|  * SPDX-License-Identifier: MIT
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a copy
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|  * of this software and associated documentation files (the "Software"), to deal
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|  * in the Software without restriction, including without limitation the rights
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|  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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|  * copies of the Software, and to permit persons to whom the Software is
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|  * furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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|  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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|  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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|  * THE SOFTWARE.
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "qemu/log.h"
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| #include "hw/i2c/bcm2835_i2c.h"
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| #include "hw/irq.h"
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| #include "migration/vmstate.h"
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| 
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| static void bcm2835_i2c_update_interrupt(BCM2835I2CState *s)
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| {
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|     int do_interrupt = 0;
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|     /* Interrupt on RXR (Needs reading) */
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|     if (s->c & BCM2835_I2C_C_INTR && s->s & BCM2835_I2C_S_RXR) {
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|         do_interrupt = 1;
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|     }
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| 
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|     /* Interrupt on TXW (Needs writing) */
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|     if (s->c & BCM2835_I2C_C_INTT && s->s & BCM2835_I2C_S_TXW) {
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|         do_interrupt = 1;
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|     }
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| 
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|     /* Interrupt on DONE (Transfer complete) */
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|     if (s->c & BCM2835_I2C_C_INTD && s->s & BCM2835_I2C_S_DONE) {
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|         do_interrupt = 1;
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|     }
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|     qemu_set_irq(s->irq, do_interrupt);
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| }
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| 
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| static void bcm2835_i2c_begin_transfer(BCM2835I2CState *s)
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| {
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|     int direction = s->c & BCM2835_I2C_C_READ;
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|     if (i2c_start_transfer(s->bus, s->a, direction)) {
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|         s->s |= BCM2835_I2C_S_ERR;
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|     }
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|     s->s |= BCM2835_I2C_S_TA;
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| 
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|     if (direction) {
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|         s->s |= BCM2835_I2C_S_RXR | BCM2835_I2C_S_RXD;
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|     } else {
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|         s->s |= BCM2835_I2C_S_TXW;
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|     }
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| }
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| 
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| static void bcm2835_i2c_finish_transfer(BCM2835I2CState *s)
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| {
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|     /*
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|      * STOP is sent when DLEN counts down to zero.
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|      *
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|      * https://github.com/torvalds/linux/blob/v6.7/drivers/i2c/busses/i2c-bcm2835.c#L223-L261
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|      * It is possible to initiate repeated starts on real hardware.
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|      * However, this requires sending another ST request before the bytes in
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|      * TX FIFO are shifted out.
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|      *
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|      * This is not emulated currently.
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|      */
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|     i2c_end_transfer(s->bus);
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|     s->s |= BCM2835_I2C_S_DONE;
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| 
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|     /* Ensure RXD is cleared, otherwise the driver registers an error */
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|     s->s &= ~(BCM2835_I2C_S_TA | BCM2835_I2C_S_RXR |
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|               BCM2835_I2C_S_TXW | BCM2835_I2C_S_RXD);
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| }
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| 
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| static uint64_t bcm2835_i2c_read(void *opaque, hwaddr addr, unsigned size)
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| {
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|     BCM2835I2CState *s = opaque;
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|     uint32_t readval = 0;
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| 
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|     switch (addr) {
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|     case BCM2835_I2C_C:
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|         readval = s->c;
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|         break;
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|     case BCM2835_I2C_S:
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|         readval = s->s;
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|         break;
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|     case BCM2835_I2C_DLEN:
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|         readval = s->dlen;
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|         break;
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|     case BCM2835_I2C_A:
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|         readval = s->a;
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|         break;
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|     case BCM2835_I2C_FIFO:
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|         /* We receive I2C messages directly instead of using FIFOs */
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|         if (s->s & BCM2835_I2C_S_TA) {
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|             readval = i2c_recv(s->bus);
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|             s->dlen -= 1;
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| 
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|             if (s->dlen == 0) {
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|                 bcm2835_i2c_finish_transfer(s);
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|             }
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|         }
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|         bcm2835_i2c_update_interrupt(s);
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|         break;
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|     case BCM2835_I2C_DIV:
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|         readval = s->div;
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|         break;
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|     case BCM2835_I2C_DEL:
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|         readval = s->del;
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|         break;
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|     case BCM2835_I2C_CLKT:
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|         readval = s->clkt;
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|         break;
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|     default:
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|         qemu_log_mask(LOG_GUEST_ERROR,
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|                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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|     }
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| 
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|     return readval;
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| }
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| 
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| static void bcm2835_i2c_write(void *opaque, hwaddr addr,
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|                               uint64_t value, unsigned int size)
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| {
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|     BCM2835I2CState *s = opaque;
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|     uint32_t writeval = value;
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| 
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|     switch (addr) {
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|     case BCM2835_I2C_C:
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|         /* ST is a one-shot operation; it must read back as 0 */
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|         s->c = writeval & ~BCM2835_I2C_C_ST;
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| 
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|         /* Start transfer */
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|         if (writeval & (BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN)) {
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|             bcm2835_i2c_begin_transfer(s);
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|             /*
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|              * Handle special case where transfer starts with zero data length.
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|              * Required for zero length i2c quick messages to work.
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|              */
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|             if (s->dlen == 0) {
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|                 bcm2835_i2c_finish_transfer(s);
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|             }
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|         }
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| 
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|         bcm2835_i2c_update_interrupt(s);
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|         break;
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|     case BCM2835_I2C_S:
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|         if (writeval & BCM2835_I2C_S_DONE && s->s & BCM2835_I2C_S_DONE) {
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|             /* When DONE is cleared, DLEN should read last written value. */
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|             s->dlen = s->last_dlen;
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|         }
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| 
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|         /* Clear DONE, CLKT and ERR by writing 1 */
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|         s->s &= ~(writeval & (BCM2835_I2C_S_DONE |
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|                   BCM2835_I2C_S_ERR | BCM2835_I2C_S_CLKT));
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|         break;
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|     case BCM2835_I2C_DLEN:
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|         s->dlen = writeval;
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|         s->last_dlen = writeval;
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|         break;
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|     case BCM2835_I2C_A:
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|         s->a = writeval;
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|         break;
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|     case BCM2835_I2C_FIFO:
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|         /* We send I2C messages directly instead of using FIFOs */
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|         if (s->s & BCM2835_I2C_S_TA) {
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|             if (s->s & BCM2835_I2C_S_TXD) {
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|                 if (!i2c_send(s->bus, writeval & 0xff)) {
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|                     s->dlen -= 1;
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|                 } else {
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|                     s->s |= BCM2835_I2C_S_ERR;
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|                 }
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|             }
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| 
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|             if (s->dlen == 0) {
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|                 bcm2835_i2c_finish_transfer(s);
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|             }
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|         }
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|         bcm2835_i2c_update_interrupt(s);
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|         break;
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|     case BCM2835_I2C_DIV:
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|         s->div = writeval;
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|         break;
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|     case BCM2835_I2C_DEL:
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|         s->del = writeval;
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|         break;
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|     case BCM2835_I2C_CLKT:
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|         s->clkt = writeval;
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|         break;
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|     default:
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|         qemu_log_mask(LOG_GUEST_ERROR,
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|                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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|     }
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| }
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| 
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| static const MemoryRegionOps bcm2835_i2c_ops = {
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|     .read = bcm2835_i2c_read,
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|     .write = bcm2835_i2c_write,
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|     .endianness = DEVICE_NATIVE_ENDIAN,
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|     .valid = {
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|         .min_access_size = 4,
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|         .max_access_size = 4,
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|     },
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| };
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| 
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| static void bcm2835_i2c_realize(DeviceState *dev, Error **errp)
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| {
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|     BCM2835I2CState *s = BCM2835_I2C(dev);
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|     s->bus = i2c_init_bus(dev, NULL);
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| 
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|     memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_i2c_ops, s,
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|                           TYPE_BCM2835_I2C, 0x24);
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|     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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|     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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| }
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| 
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| static void bcm2835_i2c_reset(DeviceState *dev)
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| {
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|     BCM2835I2CState *s = BCM2835_I2C(dev);
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| 
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|     /* Reset values according to BCM2835 Peripheral Documentation */
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|     s->c = 0x0;
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|     s->s = BCM2835_I2C_S_TXD | BCM2835_I2C_S_TXE;
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|     s->dlen = 0x0;
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|     s->a = 0x0;
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|     s->div = 0x5dc;
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|     s->del = 0x00300030;
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|     s->clkt = 0x40;
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| }
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| 
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| static const VMStateDescription vmstate_bcm2835_i2c = {
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|     .name = TYPE_BCM2835_I2C,
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|     .version_id = 1,
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|     .minimum_version_id = 1,
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|     .fields = (const VMStateField[]) {
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|         VMSTATE_UINT32(c, BCM2835I2CState),
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|         VMSTATE_UINT32(s, BCM2835I2CState),
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|         VMSTATE_UINT32(dlen, BCM2835I2CState),
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|         VMSTATE_UINT32(a, BCM2835I2CState),
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|         VMSTATE_UINT32(div, BCM2835I2CState),
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|         VMSTATE_UINT32(del, BCM2835I2CState),
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|         VMSTATE_UINT32(clkt, BCM2835I2CState),
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|         VMSTATE_UINT32(last_dlen, BCM2835I2CState),
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|         VMSTATE_END_OF_LIST()
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|     }
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| };
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| 
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| static void bcm2835_i2c_class_init(ObjectClass *klass, void *data)
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| {
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|     DeviceClass *dc = DEVICE_CLASS(klass);
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| 
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|     device_class_set_legacy_reset(dc, bcm2835_i2c_reset);
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|     dc->realize = bcm2835_i2c_realize;
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|     dc->vmsd = &vmstate_bcm2835_i2c;
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| }
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| 
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| static const TypeInfo bcm2835_i2c_info = {
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|     .name = TYPE_BCM2835_I2C,
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|     .parent = TYPE_SYS_BUS_DEVICE,
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|     .instance_size = sizeof(BCM2835I2CState),
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|     .class_init = bcm2835_i2c_class_init,
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| };
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| 
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| static void bcm2835_i2c_register_types(void)
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| {
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|     type_register_static(&bcm2835_i2c_info);
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| }
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| 
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| type_init(bcm2835_i2c_register_types)
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