1e5a7c57a5
The Octeon68XX CPU is available since commit 9a6046a655
("target/mips: introduce Cavium Octeon CPU model").
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722
Reported-by: Johnathan Hữu Trí <nhtri2003@gmail.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240814133928.6746-3-philmd@linaro.org>
26 lines
707 B
C
26 lines
707 B
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or (at your option) any
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* later version. See the COPYING file in the top-level directory.
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*/
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#ifndef MIPS64_TARGET_ELF_H
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#define MIPS64_TARGET_ELF_H
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static inline const char *cpu_get_model(uint32_t eflags)
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{
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switch (eflags & EF_MIPS_MACH) {
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case EF_MIPS_MACH_OCTEON:
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case EF_MIPS_MACH_OCTEON2:
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case EF_MIPS_MACH_OCTEON3:
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return "Octeon68XX";
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default:
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break;
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}
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if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) {
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return "I6400";
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}
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return "5KEf";
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}
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#endif
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