ths 1b6fd0bc55 Restrict CP0_PerfCnt to legal values. ...

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3476 c046a42c-6fe2-441c-8c8c-71466251a162

2007-10-29 00:49:32 +00:00

..

cpu.h

Implement missing MIPS supervisor mode bits.

2007-10-28 19:45:05 +00:00

exec.h

Implement missing MIPS supervisor mode bits.

2007-10-28 19:45:05 +00:00

fop_template.c

find -type f | xargs sed -i 's/[\t ]$//g' # on most files

2007-09-16 21:08:06 +00:00

helper.c

Implement missing MIPS supervisor mode bits.

2007-10-28 19:45:05 +00:00

mips-defs.h

Use the standard ASE check for MIPS-3D and MT.

2007-10-23 17:04:27 +00:00

op_helper.c

Implement missing MIPS supervisor mode bits.

2007-10-28 19:45:05 +00:00

op_mem.c

Enforce proper sign extension for lwl/lwr on MIPS64.

2007-10-23 23:23:43 +00:00

op_template.c

Code provision for n32/n64 mips userland emulation. Not functional yet.

2007-09-30 01:58:33 +00:00

op.c

Restrict CP0_PerfCnt to legal values.

2007-10-29 00:49:32 +00:00

TODO

Update TODO.

2007-10-17 13:43:58 +00:00

translate_init.c

Use the standard ASE check for MIPS-3D and MT.

2007-10-23 17:04:27 +00:00

translate.c

Implement missing MIPS supervisor mode bits.

2007-10-28 19:45:05 +00:00