0c54acb824
The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V IOMMU. It includes support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4, sv39x4, sv48x4, sv57x4 caps). Other capabilities like ATS and DBG support will be added incrementally in the next patches. Co-developed-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jason Chien <jason.chien@sifive.com> Message-ID: <20241016204038.649340-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
364 lines
14 KiB
C
364 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2022-2023 Rivos Inc.
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* Copyright © 2023 FORTH-ICS/CARV
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* Copyright © 2023 RISC-V IOMMU Task Group
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*
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* RISC-V IOMMU - Register Layout and Data Structures.
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*
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* Based on the IOMMU spec version 1.0, 3/2023
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* https://github.com/riscv-non-isa/riscv-iommu
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*/
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#ifndef HW_RISCV_IOMMU_BITS_H
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#define HW_RISCV_IOMMU_BITS_H
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#define RISCV_IOMMU_SPEC_DOT_VER 0x010
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#ifndef GENMASK_ULL
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#define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l))
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#endif
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/*
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* struct riscv_iommu_fq_record - Fault/Event Queue Record
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* See section 3.2 for more info.
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*/
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struct riscv_iommu_fq_record {
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uint64_t hdr;
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uint64_t _reserved;
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uint64_t iotval;
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uint64_t iotval2;
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};
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/* Header fields */
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#define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0)
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#define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12)
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#define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32)
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#define RISCV_IOMMU_FQ_HDR_TTYPE GENMASK_ULL(39, 34)
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#define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40)
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/*
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* struct riscv_iommu_pq_record - PCIe Page Request record
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* For more infos on the PCIe Page Request queue see chapter 3.3.
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*/
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struct riscv_iommu_pq_record {
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uint64_t hdr;
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uint64_t payload;
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};
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/* Header fields */
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#define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12)
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#define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32)
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#define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33)
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#define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34)
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#define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40)
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/* Payload fields */
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#define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0)
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/* Common field positions */
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#define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10)
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#define RISCV_IOMMU_QUEUE_LOGSZ_FIELD GENMASK_ULL(4, 0)
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#define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0)
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#define RISCV_IOMMU_QUEUE_ENABLE BIT(0)
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#define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1)
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#define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8)
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#define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9)
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#define RISCV_IOMMU_QUEUE_ACTIVE BIT(16)
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#define RISCV_IOMMU_QUEUE_BUSY BIT(17)
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#define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0)
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#define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60)
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/* 5.3 IOMMU Capabilities (64bits) */
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#define RISCV_IOMMU_REG_CAP 0x0000
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#define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0)
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#define RISCV_IOMMU_CAP_SV32 BIT_ULL(8)
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#define RISCV_IOMMU_CAP_SV39 BIT_ULL(9)
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#define RISCV_IOMMU_CAP_SV48 BIT_ULL(10)
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#define RISCV_IOMMU_CAP_SV57 BIT_ULL(11)
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#define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16)
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#define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17)
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#define RISCV_IOMMU_CAP_SV48X4 BIT_ULL(18)
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#define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19)
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#define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22)
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#define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23)
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#define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26)
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#define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28)
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#define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32)
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#define RISCV_IOMMU_CAP_PD8 BIT_ULL(38)
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#define RISCV_IOMMU_CAP_PD17 BIT_ULL(39)
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#define RISCV_IOMMU_CAP_PD20 BIT_ULL(40)
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/* 5.4 Features control register (32bits) */
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#define RISCV_IOMMU_REG_FCTL 0x0008
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#define RISCV_IOMMU_FCTL_BE BIT(0)
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#define RISCV_IOMMU_FCTL_WSI BIT(1)
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#define RISCV_IOMMU_FCTL_GXL BIT(2)
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/* 5.5 Device-directory-table pointer (64bits) */
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#define RISCV_IOMMU_REG_DDTP 0x0010
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#define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0)
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#define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4)
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#define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD
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enum riscv_iommu_ddtp_modes {
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RISCV_IOMMU_DDTP_MODE_OFF = 0,
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RISCV_IOMMU_DDTP_MODE_BARE = 1,
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RISCV_IOMMU_DDTP_MODE_1LVL = 2,
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RISCV_IOMMU_DDTP_MODE_2LVL = 3,
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RISCV_IOMMU_DDTP_MODE_3LVL = 4,
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RISCV_IOMMU_DDTP_MODE_MAX = 4
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};
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/* 5.6 Command Queue Base (64bits) */
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#define RISCV_IOMMU_REG_CQB 0x0018
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#define RISCV_IOMMU_CQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD
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#define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD
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/* 5.7 Command Queue head (32bits) */
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#define RISCV_IOMMU_REG_CQH 0x0020
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/* 5.8 Command Queue tail (32bits) */
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#define RISCV_IOMMU_REG_CQT 0x0024
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/* 5.9 Fault Queue Base (64bits) */
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#define RISCV_IOMMU_REG_FQB 0x0028
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#define RISCV_IOMMU_FQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD
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#define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD
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/* 5.10 Fault Queue Head (32bits) */
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#define RISCV_IOMMU_REG_FQH 0x0030
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/* 5.11 Fault Queue tail (32bits) */
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#define RISCV_IOMMU_REG_FQT 0x0034
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/* 5.12 Page Request Queue base (64bits) */
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#define RISCV_IOMMU_REG_PQB 0x0038
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#define RISCV_IOMMU_PQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD
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#define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD
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/* 5.13 Page Request Queue head (32bits) */
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#define RISCV_IOMMU_REG_PQH 0x0040
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/* 5.14 Page Request Queue tail (32bits) */
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#define RISCV_IOMMU_REG_PQT 0x0044
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/* 5.15 Command Queue CSR (32bits) */
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#define RISCV_IOMMU_REG_CQCSR 0x0048
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#define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT
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#define RISCV_IOMMU_CQCSR_CMD_TO BIT(9)
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#define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10)
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#define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11)
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#define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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/* 5.16 Fault Queue CSR (32bits) */
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#define RISCV_IOMMU_REG_FQCSR 0x004C
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#define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT
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#define RISCV_IOMMU_FQCSR_FQOF RISCV_IOMMU_QUEUE_OVERFLOW
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#define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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/* 5.17 Page Request Queue CSR (32bits) */
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#define RISCV_IOMMU_REG_PQCSR 0x0050
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#define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE
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#define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE
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#define RISCV_IOMMU_PQCSR_PQMF RISCV_IOMMU_QUEUE_MEM_FAULT
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#define RISCV_IOMMU_PQCSR_PQOF RISCV_IOMMU_QUEUE_OVERFLOW
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#define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE
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#define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY
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/* 5.18 Interrupt Pending Status (32bits) */
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#define RISCV_IOMMU_REG_IPSR 0x0054
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#define RISCV_IOMMU_IPSR_CIP BIT(0)
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#define RISCV_IOMMU_IPSR_FIP BIT(1)
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#define RISCV_IOMMU_IPSR_PIP BIT(3)
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enum {
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RISCV_IOMMU_INTR_CQ,
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RISCV_IOMMU_INTR_FQ,
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RISCV_IOMMU_INTR_PM,
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RISCV_IOMMU_INTR_PQ,
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RISCV_IOMMU_INTR_COUNT
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};
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/* 5.27 Interrupt cause to vector (64bits) */
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#define RISCV_IOMMU_REG_ICVEC 0x02F8
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#define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0)
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#define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4)
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#define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8)
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#define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12)
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/* 5.28 MSI Configuration table (32 * 64bits) */
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#define RISCV_IOMMU_REG_MSI_CONFIG 0x0300
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#define RISCV_IOMMU_REG_SIZE 0x1000
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#define RISCV_IOMMU_DDTE_VALID BIT_ULL(0)
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#define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD
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/* Struct riscv_iommu_dc - Device Context - section 2.1 */
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struct riscv_iommu_dc {
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uint64_t tc;
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uint64_t iohgatp;
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uint64_t ta;
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uint64_t fsc;
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uint64_t msiptp;
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uint64_t msi_addr_mask;
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uint64_t msi_addr_pattern;
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uint64_t _reserved;
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};
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/* Translation control fields */
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#define RISCV_IOMMU_DC_TC_V BIT_ULL(0)
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#define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2)
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#define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3)
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#define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4)
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#define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5)
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#define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6)
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#define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7)
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#define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8)
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#define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9)
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#define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10)
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#define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11)
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/* Second-stage (aka G-stage) context fields */
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#define RISCV_IOMMU_DC_IOHGATP_PPN RISCV_IOMMU_ATP_PPN_FIELD
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#define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44)
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#define RISCV_IOMMU_DC_IOHGATP_MODE RISCV_IOMMU_ATP_MODE_FIELD
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enum riscv_iommu_dc_iohgatp_modes {
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RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0,
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RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8,
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RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8,
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RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9,
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RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10
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};
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/* Translation attributes fields */
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#define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12)
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/* First-stage context fields */
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#define RISCV_IOMMU_DC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD
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#define RISCV_IOMMU_DC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD
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/* Generic I/O MMU command structure - check section 3.1 */
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struct riscv_iommu_command {
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uint64_t dword0;
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uint64_t dword1;
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};
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#define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0)
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#define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7)
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#define RISCV_IOMMU_CMD_IOTINVAL_OPCODE 1
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#define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA 0
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#define RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA 1
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#define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10)
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#define RISCV_IOMMU_CMD_IOTINVAL_PSCID GENMASK_ULL(31, 12)
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#define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32)
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#define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33)
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#define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44)
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#define RISCV_IOMMU_CMD_IOFENCE_OPCODE 2
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#define RISCV_IOMMU_CMD_IOFENCE_FUNC_C 0
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#define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10)
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#define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32)
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#define RISCV_IOMMU_CMD_IODIR_OPCODE 3
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#define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT 0
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#define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT 1
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#define RISCV_IOMMU_CMD_IODIR_PID GENMASK_ULL(31, 12)
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#define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33)
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#define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40)
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enum riscv_iommu_dc_fsc_atp_modes {
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RISCV_IOMMU_DC_FSC_MODE_BARE = 0,
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RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8,
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RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8,
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RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9,
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RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10,
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RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1,
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RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2,
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RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3
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};
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enum riscv_iommu_fq_causes {
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RISCV_IOMMU_FQ_CAUSE_INST_FAULT = 1,
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RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED = 4,
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RISCV_IOMMU_FQ_CAUSE_RD_FAULT = 5,
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RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED = 6,
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RISCV_IOMMU_FQ_CAUSE_WR_FAULT = 7,
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RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S = 12,
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RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S = 13,
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RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S = 15,
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RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS = 20,
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RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS = 21,
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RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS = 23,
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RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED = 256,
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RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT = 257,
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RISCV_IOMMU_FQ_CAUSE_DDT_INVALID = 258,
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RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259,
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RISCV_IOMMU_FQ_CAUSE_TTYPE_BLOCKED = 260,
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RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT = 261,
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RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262,
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RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED = 263,
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RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT = 264,
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RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT = 265,
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RISCV_IOMMU_FQ_CAUSE_PDT_INVALID = 266,
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RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED = 267,
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RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED = 268,
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RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED = 269,
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RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED = 270,
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RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED = 271,
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RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR = 272,
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RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT = 273,
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RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED = 274
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};
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/* MSI page table pointer */
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#define RISCV_IOMMU_DC_MSIPTP_PPN RISCV_IOMMU_ATP_PPN_FIELD
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#define RISCV_IOMMU_DC_MSIPTP_MODE RISCV_IOMMU_ATP_MODE_FIELD
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#define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0
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#define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1
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/* Translation attributes fields */
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#define RISCV_IOMMU_PC_TA_V BIT_ULL(0)
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#define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32)
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/* First stage context fields */
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#define RISCV_IOMMU_PC_FSC_PPN GENMASK_ULL(43, 0)
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#define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44)
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enum riscv_iommu_fq_ttypes {
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RISCV_IOMMU_FQ_TTYPE_NONE = 0,
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RISCV_IOMMU_FQ_TTYPE_UADDR_INST_FETCH = 1,
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RISCV_IOMMU_FQ_TTYPE_UADDR_RD = 2,
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RISCV_IOMMU_FQ_TTYPE_UADDR_WR = 3,
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RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH = 5,
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RISCV_IOMMU_FQ_TTYPE_TADDR_RD = 6,
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RISCV_IOMMU_FQ_TTYPE_TADDR_WR = 7,
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RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 8,
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};
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/* Fields on pte */
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#define RISCV_IOMMU_MSI_PTE_V BIT_ULL(0)
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#define RISCV_IOMMU_MSI_PTE_M GENMASK_ULL(2, 1)
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#define RISCV_IOMMU_MSI_PTE_M_MRIF 1
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#define RISCV_IOMMU_MSI_PTE_M_BASIC 3
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/* When M == 1 (MRIF mode) */
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#define RISCV_IOMMU_MSI_PTE_MRIF_ADDR GENMASK_ULL(53, 7)
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/* When M == 3 (basic mode) */
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#define RISCV_IOMMU_MSI_PTE_PPN RISCV_IOMMU_PPN_FIELD
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#define RISCV_IOMMU_MSI_PTE_C BIT_ULL(63)
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/* Fields on mrif_info */
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#define RISCV_IOMMU_MSI_MRIF_NID GENMASK_ULL(9, 0)
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#define RISCV_IOMMU_MSI_MRIF_NPPN RISCV_IOMMU_PPN_FIELD
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#define RISCV_IOMMU_MSI_MRIF_NID_MSB BIT_ULL(60)
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#endif /* _RISCV_IOMMU_BITS_H_ */
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