ac4330359b
In the PC machine, the PIT is created in board code to allow it to be virtualized with various virtualization techniques. So explicitly disable its creation in the PC machine via a property which defaults to enabled. Once the PIIX implementations are consolidated this default will keep Malta working without further ado. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-22-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
85 lines
2.1 KiB
C
85 lines
2.1 KiB
C
/*
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* QEMU PIIX South Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2018 Hervé Poussineau
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef HW_SOUTHBRIDGE_PIIX_H
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#define HW_SOUTHBRIDGE_PIIX_H
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#include "hw/pci/pci_device.h"
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#include "hw/acpi/piix4.h"
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#include "hw/ide/pci.h"
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#include "hw/rtc/mc146818rtc.h"
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#include "hw/usb/hcd-uhci.h"
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/* PIRQRC[A:D]: PIRQx Route Control Registers */
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#define PIIX_PIRQCA 0x60
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#define PIIX_PIRQCB 0x61
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#define PIIX_PIRQCC 0x62
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#define PIIX_PIRQCD 0x63
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/*
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* Reset Control Register: PCI-accessible ISA-Compatible Register at address
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* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
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*/
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#define PIIX_RCR_IOPORT 0xcf9
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
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struct PIIXState {
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PCIDevice dev;
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/*
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* bitmap to track pic levels.
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* The pic level is the logical OR of all the PCI irqs mapped to it
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * ISA_NUM_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if ISA_NUM_IRQS * PIIX_NUM_PIRQS > 64
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#error "unable to encode pic state in 64bit in pic_levels."
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#endif
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uint64_t pic_levels;
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qemu_irq cpu_intr;
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qemu_irq isa_irqs_in[ISA_NUM_IRQS];
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
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MC146818RtcState rtc;
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PCIIDEState ide;
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UHCIState uhci;
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PIIX4PMState pm;
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uint32_t smb_io_base;
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/* Reset Control Register contents */
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uint8_t rcr;
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/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
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MemoryRegion rcr_mem;
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bool has_acpi;
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bool has_pic;
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bool has_pit;
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bool has_usb;
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bool smm_enabled;
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};
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#define TYPE_PIIX_PCI_DEVICE "pci-piix"
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OBJECT_DECLARE_SIMPLE_TYPE(PIIXState, PIIX_PCI_DEVICE)
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#define TYPE_PIIX3_DEVICE "PIIX3"
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#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
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#endif
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