ea86e4e600
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4190 c046a42c-6fe2-441c-8c8c-71466251a162
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
#include "hw.h"
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#include "mips.h"
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#include "qemu-timer.h"
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#define TIMER_FREQ 100 * 1000 * 1000
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void cpu_mips_irqctrl_init (void)
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{
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}
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/* XXX: do not use a global */
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uint32_t cpu_mips_get_random (CPUState *env)
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{
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static uint32_t seed = 0;
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uint32_t idx;
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seed = seed * 314159 + 1;
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idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
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return idx;
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}
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/* MIPS R4K timer */
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uint32_t cpu_mips_get_count (CPUState *env)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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return env->CP0_Count;
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else
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return env->CP0_Count +
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(uint32_t)muldiv64(qemu_get_clock(vm_clock),
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TIMER_FREQ, ticks_per_sec);
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}
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static void cpu_mips_timer_update(CPUState *env)
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{
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uint64_t now, next;
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uint32_t wait;
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now = qemu_get_clock(vm_clock);
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wait = env->CP0_Compare - env->CP0_Count -
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(uint32_t)muldiv64(now, TIMER_FREQ, ticks_per_sec);
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next = now + muldiv64(wait, ticks_per_sec, TIMER_FREQ);
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qemu_mod_timer(env->timer, next);
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}
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void cpu_mips_store_count (CPUState *env, uint32_t count)
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{
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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env->CP0_Count = count;
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else {
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/* Store new count register */
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env->CP0_Count =
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count - (uint32_t)muldiv64(qemu_get_clock(vm_clock),
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TIMER_FREQ, ticks_per_sec);
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/* Update timer timer */
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cpu_mips_timer_update(env);
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}
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}
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void cpu_mips_store_compare (CPUState *env, uint32_t value)
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{
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env->CP0_Compare = value;
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if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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env->CP0_Cause &= ~(1 << CP0Ca_TI);
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qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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void cpu_mips_start_count(CPUState *env)
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{
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cpu_mips_store_count(env, env->CP0_Count);
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}
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void cpu_mips_stop_count(CPUState *env)
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{
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/* Store the current value */
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env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),
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TIMER_FREQ, ticks_per_sec);
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}
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static void mips_timer_cb (void *opaque)
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{
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CPUState *env;
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env = opaque;
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#if 0
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if (logfile) {
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fprintf(logfile, "%s\n", __func__);
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}
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#endif
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if (env->CP0_Cause & (1 << CP0Ca_DC))
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return;
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cpu_mips_timer_update(env);
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if (env->insn_flags & ISA_MIPS32R2)
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env->CP0_Cause |= 1 << CP0Ca_TI;
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qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
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}
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void cpu_mips_clock_init (CPUState *env)
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{
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env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
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env->CP0_Compare = 0;
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cpu_mips_store_count(env, 1);
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}
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