1094 lines
28 KiB
C
1094 lines
28 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "trace.h"
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#include "qemu/timer.h"
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#include "hw/ppc/spapr.h"
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#include "hw/ppc/xics.h"
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#include "qemu/error-report.h"
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#include "qapi/visitor.h"
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static int get_cpu_index_by_dt_id(int cpu_dt_id)
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{
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PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
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if (cpu) {
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return cpu->parent_obj.cpu_index;
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}
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return -1;
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}
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void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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ICPState *ss = &icp->ss[cs->cpu_index];
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XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
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assert(cs->cpu_index < icp->nr_servers);
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if (info->cpu_setup) {
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info->cpu_setup(icp, cpu);
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}
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switch (PPC_INPUT(env)) {
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case PPC_FLAGS_INPUT_POWER7:
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ss->output = env->irq_inputs[POWER7_INPUT_INT];
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break;
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case PPC_FLAGS_INPUT_970:
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ss->output = env->irq_inputs[PPC970_INPUT_INT];
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break;
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default:
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error_report("XICS interrupt controller does not support this CPU "
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"bus model");
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abort();
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}
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}
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/*
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* XICS Common class - parent for emulated XICS and KVM-XICS
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*/
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static void xics_common_reset(DeviceState *d)
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{
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XICSState *icp = XICS_COMMON(d);
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int i;
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for (i = 0; i < icp->nr_servers; i++) {
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device_reset(DEVICE(&icp->ss[i]));
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}
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device_reset(DEVICE(icp->ics));
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}
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static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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XICSState *icp = XICS_COMMON(obj);
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int64_t value = icp->nr_irqs;
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visit_type_int(v, name, &value, errp);
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}
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static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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XICSState *icp = XICS_COMMON(obj);
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XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
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Error *error = NULL;
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int64_t value;
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visit_type_int(v, name, &value, &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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if (icp->nr_irqs) {
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error_setg(errp, "Number of interrupts is already set to %u",
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icp->nr_irqs);
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return;
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}
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assert(info->set_nr_irqs);
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assert(icp->ics);
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info->set_nr_irqs(icp, value, errp);
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}
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static void xics_prop_get_nr_servers(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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XICSState *icp = XICS_COMMON(obj);
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int64_t value = icp->nr_servers;
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visit_type_int(v, name, &value, errp);
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}
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static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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XICSState *icp = XICS_COMMON(obj);
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XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
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Error *error = NULL;
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int64_t value;
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visit_type_int(v, name, &value, &error);
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if (error) {
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error_propagate(errp, error);
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return;
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}
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if (icp->nr_servers) {
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error_setg(errp, "Number of servers is already set to %u",
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icp->nr_servers);
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return;
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}
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assert(info->set_nr_servers);
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info->set_nr_servers(icp, value, errp);
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}
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static void xics_common_initfn(Object *obj)
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{
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object_property_add(obj, "nr_irqs", "int",
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xics_prop_get_nr_irqs, xics_prop_set_nr_irqs,
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NULL, NULL, NULL);
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object_property_add(obj, "nr_servers", "int",
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xics_prop_get_nr_servers, xics_prop_set_nr_servers,
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NULL, NULL, NULL);
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}
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static void xics_common_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->reset = xics_common_reset;
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}
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static const TypeInfo xics_common_info = {
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.name = TYPE_XICS_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XICSState),
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.class_size = sizeof(XICSStateClass),
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.instance_init = xics_common_initfn,
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.class_init = xics_common_class_init,
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};
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/*
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* ICP: Presentation layer
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*/
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(ss) (((ss)->xirr) & XISR_MASK)
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#define CPPR(ss) (((ss)->xirr) >> 24)
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static void ics_reject(ICSState *ics, int nr);
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static void ics_resend(ICSState *ics);
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static void ics_eoi(ICSState *ics, int nr);
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static void icp_check_ipi(XICSState *icp, int server)
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{
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ICPState *ss = icp->ss + server;
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if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
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return;
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}
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trace_xics_icp_check_ipi(server, ss->mfrr);
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
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ss->pending_priority = ss->mfrr;
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qemu_irq_raise(ss->output);
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}
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static void icp_resend(XICSState *icp, int server)
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{
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ICPState *ss = icp->ss + server;
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if (ss->mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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}
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ics_resend(icp->ics);
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}
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static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
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{
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ICPState *ss = icp->ss + server;
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uint8_t old_cppr;
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uint32_t old_xisr;
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old_cppr = CPPR(ss);
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
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if (cppr < old_cppr) {
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if (XISR(ss) && (cppr <= ss->pending_priority)) {
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old_xisr = XISR(ss);
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ss->xirr &= ~XISR_MASK; /* Clear XISR */
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ss->pending_priority = 0xff;
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qemu_irq_lower(ss->output);
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ics_reject(icp->ics, old_xisr);
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}
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} else {
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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}
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static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
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{
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ICPState *ss = icp->ss + server;
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ss->mfrr = mfrr;
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if (mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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}
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}
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static uint32_t icp_accept(ICPState *ss)
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{
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uint32_t xirr = ss->xirr;
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qemu_irq_lower(ss->output);
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ss->xirr = ss->pending_priority << 24;
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ss->pending_priority = 0xff;
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trace_xics_icp_accept(xirr, ss->xirr);
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return xirr;
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}
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static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
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{
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ICPState *ss = icp->ss + server;
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/* Send EOI -> ICS */
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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trace_xics_icp_eoi(server, xirr, ss->xirr);
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ics_eoi(icp->ics, xirr & XISR_MASK);
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
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{
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ICPState *ss = icp->ss + server;
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trace_xics_icp_irq(server, nr, priority);
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if ((priority >= CPPR(ss))
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|| (XISR(ss) && (ss->pending_priority <= priority))) {
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ics_reject(icp->ics, nr);
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} else {
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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ss->pending_priority = priority;
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trace_xics_icp_raise(ss->xirr, ss->pending_priority);
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qemu_irq_raise(ss->output);
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}
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}
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static void icp_dispatch_pre_save(void *opaque)
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{
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ICPState *ss = opaque;
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ICPStateClass *info = ICP_GET_CLASS(ss);
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if (info->pre_save) {
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info->pre_save(ss);
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}
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}
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static int icp_dispatch_post_load(void *opaque, int version_id)
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{
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ICPState *ss = opaque;
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ICPStateClass *info = ICP_GET_CLASS(ss);
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if (info->post_load) {
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return info->post_load(ss, version_id);
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}
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return 0;
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}
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static const VMStateDescription vmstate_icp_server = {
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.name = "icp/server",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = icp_dispatch_pre_save,
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.post_load = icp_dispatch_post_load,
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.fields = (VMStateField[]) {
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/* Sanity check */
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VMSTATE_UINT32(xirr, ICPState),
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VMSTATE_UINT8(pending_priority, ICPState),
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VMSTATE_UINT8(mfrr, ICPState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void icp_reset(DeviceState *dev)
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{
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ICPState *icp = ICP(dev);
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icp->xirr = 0;
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icp->pending_priority = 0xff;
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icp->mfrr = 0xff;
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/* Make all outputs are deasserted */
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qemu_set_irq(icp->output, 0);
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}
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static void icp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = icp_reset;
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dc->vmsd = &vmstate_icp_server;
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}
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static const TypeInfo icp_info = {
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.name = TYPE_ICP,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(ICPState),
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.class_init = icp_class_init,
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.class_size = sizeof(ICPStateClass),
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};
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/*
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* ICS: Source layer
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*/
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static int ics_valid_irq(ICSState *ics, uint32_t nr)
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{
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return (nr >= ics->offset)
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&& (nr < (ics->offset + ics->nr_irqs));
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}
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static void resend_msi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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/* FIXME: filter by server#? */
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if (irq->status & XICS_STATUS_REJECTED) {
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irq->status &= ~XICS_STATUS_REJECTED;
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if (irq->priority != 0xff) {
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icp_irq(ics->icp, irq->server, srcno + ics->offset,
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irq->priority);
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}
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}
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}
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static void resend_lsi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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if ((irq->priority != 0xff)
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&& (irq->status & XICS_STATUS_ASSERTED)
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&& !(irq->status & XICS_STATUS_SENT)) {
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irq->status |= XICS_STATUS_SENT;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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static void set_irq_msi(ICSState *ics, int srcno, int val)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_set_irq_msi(srcno, srcno + ics->offset);
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if (val) {
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if (irq->priority == 0xff) {
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irq->status |= XICS_STATUS_MASKED_PENDING;
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trace_xics_masked_pending();
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} else {
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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}
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static void set_irq_lsi(ICSState *ics, int srcno, int val)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
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if (val) {
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irq->status |= XICS_STATUS_ASSERTED;
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} else {
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irq->status &= ~XICS_STATUS_ASSERTED;
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}
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resend_lsi(ics, srcno);
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}
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static void ics_set_irq(void *opaque, int srcno, int val)
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{
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ICSState *ics = (ICSState *)opaque;
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if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
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set_irq_lsi(ics, srcno, val);
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} else {
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set_irq_msi(ics, srcno, val);
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}
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}
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static void write_xive_msi(ICSState *ics, int srcno)
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{
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ICSIRQState *irq = ics->irqs + srcno;
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if (!(irq->status & XICS_STATUS_MASKED_PENDING)
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|| (irq->priority == 0xff)) {
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return;
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}
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irq->status &= ~XICS_STATUS_MASKED_PENDING;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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static void write_xive_lsi(ICSState *ics, int srcno)
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{
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resend_lsi(ics, srcno);
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}
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static void ics_write_xive(ICSState *ics, int nr, int server,
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uint8_t priority, uint8_t saved_priority)
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{
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int srcno = nr - ics->offset;
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ICSIRQState *irq = ics->irqs + srcno;
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irq->server = server;
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irq->priority = priority;
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irq->saved_priority = saved_priority;
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trace_xics_ics_write_xive(nr, srcno, server, priority);
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if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
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write_xive_lsi(ics, srcno);
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} else {
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write_xive_msi(ics, srcno);
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}
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}
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static void ics_reject(ICSState *ics, int nr)
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{
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ICSIRQState *irq = ics->irqs + nr - ics->offset;
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trace_xics_ics_reject(nr, nr - ics->offset);
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irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
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irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
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}
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static void ics_resend(ICSState *ics)
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{
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int i;
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for (i = 0; i < ics->nr_irqs; i++) {
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/* FIXME: filter by server#? */
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if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
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resend_lsi(ics, i);
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} else {
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resend_msi(ics, i);
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}
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}
|
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}
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|
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static void ics_eoi(ICSState *ics, int nr)
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{
|
|
int srcno = nr - ics->offset;
|
|
ICSIRQState *irq = ics->irqs + srcno;
|
|
|
|
trace_xics_ics_eoi(nr);
|
|
|
|
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
|
|
irq->status &= ~XICS_STATUS_SENT;
|
|
}
|
|
}
|
|
|
|
static void ics_reset(DeviceState *dev)
|
|
{
|
|
ICSState *ics = ICS(dev);
|
|
int i;
|
|
uint8_t flags[ics->nr_irqs];
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
flags[i] = ics->irqs[i].flags;
|
|
}
|
|
|
|
memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
|
|
|
|
for (i = 0; i < ics->nr_irqs; i++) {
|
|
ics->irqs[i].priority = 0xff;
|
|
ics->irqs[i].saved_priority = 0xff;
|
|
ics->irqs[i].flags = flags[i];
|
|
}
|
|
}
|
|
|
|
static int ics_post_load(ICSState *ics, int version_id)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ics->icp->nr_servers; i++) {
|
|
icp_resend(ics->icp, i);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void ics_dispatch_pre_save(void *opaque)
|
|
{
|
|
ICSState *ics = opaque;
|
|
ICSStateClass *info = ICS_GET_CLASS(ics);
|
|
|
|
if (info->pre_save) {
|
|
info->pre_save(ics);
|
|
}
|
|
}
|
|
|
|
static int ics_dispatch_post_load(void *opaque, int version_id)
|
|
{
|
|
ICSState *ics = opaque;
|
|
ICSStateClass *info = ICS_GET_CLASS(ics);
|
|
|
|
if (info->post_load) {
|
|
return info->post_load(ics, version_id);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_ics_irq = {
|
|
.name = "ics/irq",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(server, ICSIRQState),
|
|
VMSTATE_UINT8(priority, ICSIRQState),
|
|
VMSTATE_UINT8(saved_priority, ICSIRQState),
|
|
VMSTATE_UINT8(status, ICSIRQState),
|
|
VMSTATE_UINT8(flags, ICSIRQState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static const VMStateDescription vmstate_ics = {
|
|
.name = "ics",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.pre_save = ics_dispatch_pre_save,
|
|
.post_load = ics_dispatch_post_load,
|
|
.fields = (VMStateField[]) {
|
|
/* Sanity check */
|
|
VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
|
|
|
|
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
|
|
vmstate_ics_irq, ICSIRQState),
|
|
VMSTATE_END_OF_LIST()
|
|
},
|
|
};
|
|
|
|
static void ics_initfn(Object *obj)
|
|
{
|
|
ICSState *ics = ICS(obj);
|
|
|
|
ics->offset = XICS_IRQ_BASE;
|
|
}
|
|
|
|
static void ics_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
ICSState *ics = ICS(dev);
|
|
|
|
if (!ics->nr_irqs) {
|
|
error_setg(errp, "Number of interrupts needs to be greater 0");
|
|
return;
|
|
}
|
|
ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
|
|
ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
|
|
}
|
|
|
|
static void ics_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ICSStateClass *isc = ICS_CLASS(klass);
|
|
|
|
dc->realize = ics_realize;
|
|
dc->vmsd = &vmstate_ics;
|
|
dc->reset = ics_reset;
|
|
isc->post_load = ics_post_load;
|
|
}
|
|
|
|
static const TypeInfo ics_info = {
|
|
.name = TYPE_ICS,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(ICSState),
|
|
.class_init = ics_class_init,
|
|
.class_size = sizeof(ICSStateClass),
|
|
.instance_init = ics_initfn,
|
|
};
|
|
|
|
/*
|
|
* Exported functions
|
|
*/
|
|
static int xics_find_source(XICSState *icp, int irq)
|
|
{
|
|
int sources = 1;
|
|
int src;
|
|
|
|
/* FIXME: implement multiple sources */
|
|
for (src = 0; src < sources; ++src) {
|
|
ICSState *ics = &icp->ics[src];
|
|
if (ics_valid_irq(ics, irq)) {
|
|
return src;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
qemu_irq xics_get_qirq(XICSState *icp, int irq)
|
|
{
|
|
int src = xics_find_source(icp, irq);
|
|
|
|
if (src >= 0) {
|
|
ICSState *ics = &icp->ics[src];
|
|
return ics->qirqs[irq - ics->offset];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
|
|
{
|
|
assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
|
|
|
|
ics->irqs[srcno].flags |=
|
|
lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
|
|
}
|
|
|
|
void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
|
|
{
|
|
int src = xics_find_source(icp, irq);
|
|
ICSState *ics;
|
|
|
|
assert(src >= 0);
|
|
|
|
ics = &icp->ics[src];
|
|
ics_set_irq_type(ics, irq - ics->offset, lsi);
|
|
}
|
|
|
|
#define ICS_IRQ_FREE(ics, srcno) \
|
|
(!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
|
|
|
|
static int ics_find_free_block(ICSState *ics, int num, int alignnum)
|
|
{
|
|
int first, i;
|
|
|
|
for (first = 0; first < ics->nr_irqs; first += alignnum) {
|
|
if (num > (ics->nr_irqs - first)) {
|
|
return -1;
|
|
}
|
|
for (i = first; i < first + num; ++i) {
|
|
if (!ICS_IRQ_FREE(ics, i)) {
|
|
break;
|
|
}
|
|
}
|
|
if (i == (first + num)) {
|
|
return first;
|
|
}
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)
|
|
{
|
|
ICSState *ics = &icp->ics[src];
|
|
int irq;
|
|
|
|
if (irq_hint) {
|
|
assert(src == xics_find_source(icp, irq_hint));
|
|
if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
|
|
error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
|
|
return -1;
|
|
}
|
|
irq = irq_hint;
|
|
} else {
|
|
irq = ics_find_free_block(ics, 1, 1);
|
|
if (irq < 0) {
|
|
error_setg(errp, "can't allocate IRQ: no IRQ left");
|
|
return -1;
|
|
}
|
|
irq += ics->offset;
|
|
}
|
|
|
|
ics_set_irq_type(ics, irq - ics->offset, lsi);
|
|
trace_xics_alloc(src, irq);
|
|
|
|
return irq;
|
|
}
|
|
|
|
/*
|
|
* Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
|
|
* If align==true, aligns the first IRQ number to num.
|
|
*/
|
|
int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
|
|
Error **errp)
|
|
{
|
|
int i, first = -1;
|
|
ICSState *ics = &icp->ics[src];
|
|
|
|
assert(src == 0);
|
|
/*
|
|
* MSIMesage::data is used for storing VIRQ so
|
|
* it has to be aligned to num to support multiple
|
|
* MSI vectors. MSI-X is not affected by this.
|
|
* The hint is used for the first IRQ, the rest should
|
|
* be allocated continuously.
|
|
*/
|
|
if (align) {
|
|
assert((num == 1) || (num == 2) || (num == 4) ||
|
|
(num == 8) || (num == 16) || (num == 32));
|
|
first = ics_find_free_block(ics, num, num);
|
|
} else {
|
|
first = ics_find_free_block(ics, num, 1);
|
|
}
|
|
if (first < 0) {
|
|
error_setg(errp, "can't find a free %d-IRQ block", num);
|
|
return -1;
|
|
}
|
|
|
|
if (first >= 0) {
|
|
for (i = first; i < first + num; ++i) {
|
|
ics_set_irq_type(ics, i, lsi);
|
|
}
|
|
}
|
|
first += ics->offset;
|
|
|
|
trace_xics_alloc_block(src, first, num, lsi, align);
|
|
|
|
return first;
|
|
}
|
|
|
|
static void ics_free(ICSState *ics, int srcno, int num)
|
|
{
|
|
int i;
|
|
|
|
for (i = srcno; i < srcno + num; ++i) {
|
|
if (ICS_IRQ_FREE(ics, i)) {
|
|
trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
|
|
}
|
|
memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
|
|
}
|
|
}
|
|
|
|
void xics_free(XICSState *icp, int irq, int num)
|
|
{
|
|
int src = xics_find_source(icp, irq);
|
|
|
|
if (src >= 0) {
|
|
ICSState *ics = &icp->ics[src];
|
|
|
|
/* FIXME: implement multiple sources */
|
|
assert(src == 0);
|
|
|
|
trace_xics_ics_free(ics - icp->ics, irq, num);
|
|
ics_free(ics, irq - ics->offset, num);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Guest interfaces
|
|
*/
|
|
|
|
static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
target_ulong cppr = args[0];
|
|
|
|
icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
target_ulong server = get_cpu_index_by_dt_id(args[0]);
|
|
target_ulong mfrr = args[1];
|
|
|
|
if (server >= spapr->icp->nr_servers) {
|
|
return H_PARAMETER;
|
|
}
|
|
|
|
icp_set_mfrr(spapr->icp, server, mfrr);
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
|
|
|
|
args[0] = xirr;
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
ICPState *ss = &spapr->icp->ss[cs->cpu_index];
|
|
uint32_t xirr = icp_accept(ss);
|
|
|
|
args[0] = xirr;
|
|
args[1] = cpu_get_host_ticks();
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
target_ulong xirr = args[0];
|
|
|
|
icp_eoi(spapr->icp, cs->cpu_index, xirr);
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
target_ulong opcode, target_ulong *args)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
ICPState *ss = &spapr->icp->ss[cs->cpu_index];
|
|
|
|
args[0] = ss->xirr;
|
|
args[1] = ss->mfrr;
|
|
|
|
return H_SUCCESS;
|
|
}
|
|
|
|
static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
uint32_t token,
|
|
uint32_t nargs, target_ulong args,
|
|
uint32_t nret, target_ulong rets)
|
|
{
|
|
ICSState *ics = spapr->icp->ics;
|
|
uint32_t nr, server, priority;
|
|
|
|
if ((nargs != 3) || (nret != 1)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
nr = rtas_ld(args, 0);
|
|
server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
|
|
priority = rtas_ld(args, 2);
|
|
|
|
if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
|
|
|| (priority > 0xff)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
ics_write_xive(ics, nr, server, priority, priority);
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
}
|
|
|
|
static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
uint32_t token,
|
|
uint32_t nargs, target_ulong args,
|
|
uint32_t nret, target_ulong rets)
|
|
{
|
|
ICSState *ics = spapr->icp->ics;
|
|
uint32_t nr;
|
|
|
|
if ((nargs != 1) || (nret != 3)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
|
|
rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
|
|
}
|
|
|
|
static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
uint32_t token,
|
|
uint32_t nargs, target_ulong args,
|
|
uint32_t nret, target_ulong rets)
|
|
{
|
|
ICSState *ics = spapr->icp->ics;
|
|
uint32_t nr;
|
|
|
|
if ((nargs != 1) || (nret != 1)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
|
|
ics->irqs[nr - ics->offset].priority);
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
}
|
|
|
|
static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
|
|
uint32_t token,
|
|
uint32_t nargs, target_ulong args,
|
|
uint32_t nret, target_ulong rets)
|
|
{
|
|
ICSState *ics = spapr->icp->ics;
|
|
uint32_t nr;
|
|
|
|
if ((nargs != 1) || (nret != 1)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
nr = rtas_ld(args, 0);
|
|
|
|
if (!ics_valid_irq(ics, nr)) {
|
|
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
|
|
return;
|
|
}
|
|
|
|
ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
|
|
ics->irqs[nr - ics->offset].saved_priority,
|
|
ics->irqs[nr - ics->offset].saved_priority);
|
|
|
|
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
|
|
}
|
|
|
|
/*
|
|
* XICS
|
|
*/
|
|
|
|
static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
|
|
{
|
|
icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
|
|
}
|
|
|
|
static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
|
|
Error **errp)
|
|
{
|
|
int i;
|
|
|
|
icp->nr_servers = nr_servers;
|
|
|
|
icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
|
|
for (i = 0; i < icp->nr_servers; i++) {
|
|
char buffer[32];
|
|
object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
|
|
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
|
|
object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
|
|
errp);
|
|
}
|
|
}
|
|
|
|
static void xics_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
XICSState *icp = XICS(dev);
|
|
Error *error = NULL;
|
|
int i;
|
|
|
|
if (!icp->nr_servers) {
|
|
error_setg(errp, "Number of servers needs to be greater 0");
|
|
return;
|
|
}
|
|
|
|
/* Registration of global state belongs into realize */
|
|
spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
|
|
spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
|
|
spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
|
|
spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
|
|
|
|
spapr_register_hypercall(H_CPPR, h_cppr);
|
|
spapr_register_hypercall(H_IPI, h_ipi);
|
|
spapr_register_hypercall(H_XIRR, h_xirr);
|
|
spapr_register_hypercall(H_XIRR_X, h_xirr_x);
|
|
spapr_register_hypercall(H_EOI, h_eoi);
|
|
spapr_register_hypercall(H_IPOLL, h_ipoll);
|
|
|
|
object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
|
|
if (error) {
|
|
error_propagate(errp, error);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < icp->nr_servers; i++) {
|
|
object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
|
|
if (error) {
|
|
error_propagate(errp, error);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void xics_initfn(Object *obj)
|
|
{
|
|
XICSState *xics = XICS(obj);
|
|
|
|
xics->ics = ICS(object_new(TYPE_ICS));
|
|
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
|
|
xics->ics->icp = xics;
|
|
}
|
|
|
|
static void xics_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
XICSStateClass *xsc = XICS_CLASS(oc);
|
|
|
|
dc->realize = xics_realize;
|
|
xsc->set_nr_irqs = xics_set_nr_irqs;
|
|
xsc->set_nr_servers = xics_set_nr_servers;
|
|
}
|
|
|
|
static const TypeInfo xics_info = {
|
|
.name = TYPE_XICS,
|
|
.parent = TYPE_XICS_COMMON,
|
|
.instance_size = sizeof(XICSState),
|
|
.class_size = sizeof(XICSStateClass),
|
|
.class_init = xics_class_init,
|
|
.instance_init = xics_initfn,
|
|
};
|
|
|
|
static void xics_register_types(void)
|
|
{
|
|
type_register_static(&xics_common_info);
|
|
type_register_static(&xics_info);
|
|
type_register_static(&ics_info);
|
|
type_register_static(&icp_info);
|
|
}
|
|
|
|
type_init(xics_register_types)
|