a8d2532645
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
127 lines
4.6 KiB
C
127 lines
4.6 KiB
C
/*
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* Altera 10M50 Nios2 GHRD
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*
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* Copyright (c) 2016 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on LabX device code
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/hw.h"
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#include "hw/char/serial.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "qemu/config-file.h"
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#include "boot.h"
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#define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb"
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static void nios2_10m50_ghrd_init(MachineState *machine)
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{
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Nios2CPU *cpu;
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DeviceState *dev;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
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MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
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MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
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MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
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ram_addr_t tcm_base = 0x0;
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ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
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ram_addr_t ram_base = 0x08000000;
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ram_addr_t ram_size = 0x08000000;
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qemu_irq *cpu_irq, irq[32];
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int i;
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/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
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memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
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&error_abort);
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memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
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phys_tcm, 0, tcm_size);
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memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
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memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
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phys_tcm_alias);
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/* Physical DRAM with alias at 0xc0000000 */
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memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
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&error_abort);
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memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
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phys_ram, 0, ram_size);
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memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
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memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
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phys_ram_alias);
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/* Create CPU -- FIXME */
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cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
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/* Register: CPU interrupt controller (PIC) */
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cpu_irq = nios2_cpu_pic_init(cpu);
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/* Register: Internal Interrupt Controller (IIC) */
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dev = qdev_create(NULL, "altera,iic");
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object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu),
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&error_abort);
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qdev_init_nofail(dev);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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/* Register: Altera 16550 UART */
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serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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/* Register: Timer sys_clk_timer */
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dev = qdev_create(NULL, "ALTR.timer");
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qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]);
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/* Register: Timer sys_clk_timer_1 */
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dev = qdev_create(NULL, "ALTR.timer");
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qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
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/* Configure new exception vectors and reset CPU for it to take effect. */
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cpu->reset_addr = 0xd4000000;
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cpu->exception_addr = 0xc8000120;
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cpu->fast_tlb_miss_addr = 0xc0000100;
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nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
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BINARY_DEVICE_TREE_FILE, NULL);
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}
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static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc)
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{
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mc->desc = "Altera 10M50 GHRD Nios II design";
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mc->init = nios2_10m50_ghrd_init;
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mc->is_default = 1;
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}
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DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init);
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