Richard Henderson 01ec3ec930 target/openrisc: Exit the TB after l.mtspr ...

A store to SR changes interrupt state, which should return
to the main loop to recognize that state.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>

2018-07-03 00:05:28 +09:00

..

alpha

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

arm

target/arm: Add ID_ISAR6

2018-06-29 15:30:54 +01:00

cris

tcg-next queue

2018-06-04 11:28:31 +01:00

hppa

tcg-next queue

2018-06-04 11:28:31 +01:00

i386

* "info mtree" improvements (Alexey)

2018-06-29 12:30:29 +01:00

lm32

tcg-next queue

2018-06-04 11:28:31 +01:00

m68k

target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn

2018-06-11 12:43:42 +02:00

microblaze

target-microblaze: Rework NOP/zero instruction handling

2018-06-15 09:05:00 +02:00

mips

target/mips: Fix gdbstub to read/write 64 bit FP registers

2018-06-27 20:13:50 +02:00

moxie

tcg-next queue

2018-06-04 11:28:31 +01:00

nios2

tcg-next queue

2018-06-04 11:28:31 +01:00

openrisc

target/openrisc: Exit the TB after l.mtspr

2018-07-03 00:05:28 +09:00

ppc

compiler: add a sizeof_field() macro

2018-06-27 13:01:40 +01:00

riscv

RISC-V: Add trailing '\n' to qemu_log() calls

2018-06-08 13:15:33 +01:00

s390x

compiler: add a sizeof_field() macro

2018-06-27 13:01:40 +01:00

sh4

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

sparc

SPARC64: add icount support

2018-06-17 11:13:06 +01:00

tilegx

tcg-next queue

2018-06-04 11:28:31 +01:00

tricore

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

unicore32

tcg: Pass tb and index to tcg_gen_exit_tb separately

2018-06-01 15:15:27 -07:00

xtensa

xtensa: Avoid calling get_page_addr_code() from helper function

2018-06-30 12:00:17 -07:00