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135 Commits

Author SHA1 Message Date
Richard Henderson
5e143c43a6 tcg-sparc: Do not remove %o[012] from 'r' constraint. 
Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-01-12 19:59:32 +00:00
Richard Henderson
7a3766f390 tcg-sparc: Implement add2, sub2, mulu2. 
Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-01-12 19:59:31 +00:00
Richard Henderson
ba225198d0 tcg-sparc: Add tcg_out_arithc. 
Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-01-12 19:59:29 +00:00
Richard Henderson
56f4927e34 tcg-sparc: Implement brcond2. 
Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-12-21 20:52:36 +00:00
Richard Henderson
a212ea7553 tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation. 
The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving __sparc_v9__ or
__sparc_v8plus__ should be reserved for something ISA related,
as with SMULX.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-12-21 20:52:34 +00:00
Richard Henderson
431722077a tcg-sparc: Improve tcg_out_movi for sparc64. 
Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-12-21 20:52:06 +00:00
Richard Henderson
4a09aa895e tcg-sparc: Fix imm13 check in movi. 
We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-12-21 20:49:34 +00:00
blueswir1
1da92db280 Fix branches and TLB matches for 64 bit targets 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-04 19:10:26 +00:00
blueswir1
f843e5282a Allocate space for static call args, increase stack frame size on Sparc64 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-04 15:33:03 +00:00
blueswir1
d4a9eb1fc6 Add some missing static and const qualifiers, reg_names only used if NDEBUG set 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-05 09:59:14 +00:00
blueswir1
9d0efc88e4 Use 64 bit loads for tlb addend only if addend size is 64 bits 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-13 20:07:53 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
blueswir1
6f41b7772d Fix 64 bit constant generation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 20:14:16 +00:00
blueswir1
90cbed4656 Fix 32 bit address overflow 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 16:13:02 +00:00
blueswir1
bffe143153 Restore AREG0 after calls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 14:34:27 +00:00
blueswir1
56fc64dfd0 Sparc code generator update (fix qemu_ld & qemu_st) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-16 19:54:01 +00:00
blueswir1
53c3748794 Sparc code generator update 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-15 18:14:44 +00:00
blueswir1
e97b640d47 Try to avoid glibc global register mangling, again 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-26 17:19:35 +00:00
blueswir1
d795eb86d7 Fix 64 bit constant generation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-07 19:34:45 +00:00
blueswir1
8384dd67fe Implement byte swapping accesses 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 11:19:24 +00:00
blueswir1
b101234a8e Implement 64-bit constant loads 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 18:09:50 +00:00
blueswir1
26cc915cff Use sethi and arith functions, fix comment 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 18:06:35 +00:00
blueswir1
57e49b4074 Fix constant checks on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 08:11:14 +00:00
blueswir1
9a7f32283c Fix qemu_ld/st branches, constification, use orcc for tst synthetic op 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 09:41:14 +00:00
blueswir1
f5ef6aacd4 Implement qemu_ld/st, fix brcond, handle more corner cases 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-16 20:15:58 +00:00
blueswir1
cf7c2ca5ff Implement brcond, ldst with large offset; fix direct jump, prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 19:44:09 +00:00
blueswir1
f02ca5cbea Fix bit fitting checks 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-15 17:30:17 +00:00
blueswir1
7d55170268 Fix compilation on Sparc host, implement ld and st 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-14 19:22:05 +00:00
aurel32
f54b3f920f HPPA (PA-RISC) host support 
(Stuart Brady)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-12 20:14:54 +00:00
blueswir1
e4d5434c3a Fix i32 memory backed variables on 64-bit host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-13 17:34:19 +00:00
blueswir1
0954d0d9e2 Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-11 21:01:02 +00:00
blueswir1
b3db875812 Add function prologue, fix pointer load on Sparc64 host 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-08 13:33:42 +00:00
blueswir1
53cd927312 Update based on Stuart Brady's comments 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-07 18:21:39 +00:00
blueswir1
2f0a500803 Fix register references (Igor Kovalenko) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-29 19:34:39 +00:00
blueswir1
8289b27975 Preliminary Sparc TCG target 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-27 17:53:27 +00:00