SYS-OSS/FRET-qemu
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237 Commits

Author SHA1 Message Date
Richard Henderson
972e35b966 target-s390: Convert DIAGNOSE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
8b5ff57115 target-s390: Convert LOAD PSW 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
7d30bb73db target-s390: Convert SET SYSTEM MASK 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
c49daa51a8 target-s390: Convert CONVERT TO DECIMAL 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
00574261e1 target-s390: Convert FP STORE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
6e764e97ca target-s390: Convert EXECUTE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
58a9e35bcc target-s390: Convert INSERT CHARACTERS UNDER MASK 
Change the CC handling to be more like TEST UNDER MASK, with val & mask.
This lets us handle ICMH much more like ICM.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
afdc70bea0 target-s390: Convert INSERT CHARACTER 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
d764a8d12b target-s390: Convert FP LOAD 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:38 -08:00
Richard Henderson
e1eaada955 target-s390: Convert MOVE LONG 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:37 -08:00
Richard Henderson
b9836c1acd target-s390: Convert SUPERVISOR CALL 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:37 -08:00
Richard Henderson
d9a3992799 target-s390: Convert SET ADDRESSING MODE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:37 -08:00
Richard Henderson
00d2dc192f target-s390: Convert TEST UNDER MASK 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:18:37 -08:00
Richard Henderson
891452e5e2 target-s390: Convert DIVIDE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:29 -08:00
Richard Henderson
c61aad6943 target-s390: Convert BRANCH ON COUNT 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:29 -08:00
Richard Henderson
7233f2ed17 target-s390: Convert BRANCH ON CONDITION 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:29 -08:00
Richard Henderson
8ac33cdb8b target-s390: Convert BRANCH AND SAVE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:29 -08:00
Richard Henderson
4e4bb43899 target-s390: Convert ADD LOGICAL CARRY and SUBTRACT LOGICAL BORROW 
I'm resonably certain that the carry/borrow-out condition for both
helpers was incorrect, failing to take into account the carry-in.
Adding the new CC_OP codes also allows removing the awkward interface
we used for the slb helpers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:29 -08:00
Richard Henderson
2b280b9708 target-s390: Convert STORE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
facfc86487 target-s390: Convert AND, OR, XOR, INSERT IMMEDIATE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
b9bca3e57a target-s390: Convert LOAD COMPLIMENT, POSITIVE, NEGATIVE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
ade9dea429 target-s390: Convert LOAD LOGICAL IMMEDIATE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
11bf2d73d0 target-s390: Convert LOAD AND TEST 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
c698d87687 target-s390: Convert LOAD (LOGICAL) BYTE, CHARACTER, HALFWORD 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
aedec19d62 target-s390: Convert LOAD ADDRESS 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
22c37a08bd target-s390: Convert LOAD, LOAD LOGICAL 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
a7e836d5eb target-s390: Convert COMPARE, COMPARE LOGICAL 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
3bbfbd1f95 target-s390: Convert AND, OR, XOR 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
1ac5889f48 target-s390: Convert 64-bit MULTIPLY LOGICAL 
Use a new "retxl" member of CPUS290XState to return the "eXtra Low" part
of a 128-bit value.  That said, this will get used when two independent
values need returning (e.g. quotient+remainder) as well.

At the same time, shuffle the elements of CPUS390XState to get this new
space from existing padding in the structure.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
d87aaf934f target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
d1c04a2ba0 target-s390: Convert MULTIPLY HALFWORD, SINGLE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
e272b3ace3 target-s390: Implement ADD LOGICAL WITH SIGNED IMMEDIATE 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
d82287dee9 target-s390: Convert ADD HALFWORD 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
d5a103cd6e target-s390: Reorg exception handling 
Make the user path more like the system path.  Prepare for more kinds
of runtime exceptions.  Rename ILC to ILEN to make it clear that we
want to pass around a full instruction length, rather than a "code"
that happens to be stored one bit left in a larger field.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:28 -08:00
Richard Henderson
3fde06f5fb target-s390: Split out disas_jcc 
Lots of duplicated code replaced with a couple of tables.  We no longer
attempt to manually invert the logic operation: the comments now match
the code.  In the fully general test, constant propagate (1 << (3 - cc))
into (8 >> cc).

The new function will be usable by non-branch insns as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
ad044d09de target-s390: Add format based disassassmbly infrastructure 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
51855ecf1a target-s390: Fix PSW_MASK handling 
We were treating psw.mask as the 32-bit quantity it is in ESA mode.
In particular, the CC field was at the wrong place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
2f22e2ec79 target-s390: Tidy unconditional BRCL 
Yes, we're about to rewrite all of this, but having this unconditional
jump recompute cc_op is a large source of "false diff errors" when
trying to examine before and after dumps.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
9d126faf42 target-s390: Fix BCR 
There were are two exit paths for which we forgot to
copy s->cc_op back to the tcg register.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
afd43fecfe target-s390: Fix SACF exit 
DISAS_EXCP is exit via exception; we wanted DISAS_JUMP.
This matters when we start cleaning up the TB exit paths.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
7e68da2a9d target-s390: Register helpers 
Which highlights a lot of cc helpers that no longer exist.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
431253c28f target-s390: Use TCG registers for FPR 
At the same time, tidy other usages of tcg_gen_deposit_i64.
In some cases we can "type cast" rather than extend, and in
others we can allow tcg_gen_deposit_i64 itself to optimize
the HOST_LONG_BITS==32 case.

Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Richard Henderson
063eb0f303 target-s390: Add missing temp_free in gen_op_calc_cc 
Signed-off-by: Richard Henderson <rth@twiddle.net>
 2013-01-05 12:00:27 -08:00
Paolo Bonzini
1de7afc984 misc: move include files to include/qemu/ 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2012-12-19 08:32:39 +01:00
Paolo Bonzini
022c62cbbc exec: move include files to include/exec/ 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2012-12-19 08:31:31 +01:00
Paolo Bonzini
76cad71136 build: kill libdis, move disassemblers to disas/ 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2012-12-19 08:29:06 +01:00
Evgeny Voevodin
ab1103def4 TCG: Use gen_opc_instr_start from context instead of global variable. 
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2012-12-08 14:24:43 +00:00
Evgeny Voevodin
c9c99c22d5 TCG: Use gen_opc_icount from context instead of global variable. 
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2012-12-08 14:24:42 +00:00
Evgeny Voevodin
25983cad31 TCG: Use gen_opc_pc from context instead of global variable. 
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2012-12-08 14:24:42 +00:00
Evgeny Voevodin
92414b31e7 TCG: Use gen_opc_buf from context instead of global variable. 
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2012-11-17 13:53:36 +00:00