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target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0

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According to the Vector Reduction Operations section in the RISC-V "V"
Vector Extension spec,
"If vl=0, no operation is performed and the destination register is not
updated."

The vd should be updated when vl is larger than 0.

Fixes: fe5c9ab1fc ("target/riscv: vector single-width integer reduction instructions")
Fixes: f714361ed7 ("target/riscv: rvv-1.0: implement vstart CSR")
Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250124101452.2519171-1-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Max Chou 2025-01-24 18:14:47 +08:00 committed by Alistair Francis
parent b55538ea22
commit ffd455963f
1 changed files with 6 additions and 2 deletions
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8
target/riscv/vector_helper.c
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@ -4659,7 +4659,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
} \ } \
s1 = OP(s1, (TD)s2); \ s1 = OP(s1, (TD)s2); \
} \ } \
*((TD *)vd + HD(0)) = s1; \ if (vl > 0) { \
*((TD *)vd + HD(0)) = s1; \
} \
env->vstart = 0; \ env->vstart = 0; \
/* set tail elements to 1s */ \ /* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, esz, vlenb); \ vext_set_elems_1s(vd, vta, esz, vlenb); \
@ -4745,7 +4747,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
} \ } \
s1 = OP(s1, (TD)s2, &env->fp_status); \ s1 = OP(s1, (TD)s2, &env->fp_status); \
} \ } \
*((TD *)vd + HD(0)) = s1; \ if (vl > 0) { \
*((TD *)vd + HD(0)) = s1; \
} \
env->vstart = 0; \ env->vstart = 0; \
/* set tail elements to 1s */ \ /* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, esz, vlenb); \ vext_set_elems_1s(vd, vta, esz, vlenb); \